This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

A LDPC decoder includes: a coded information receiving circuit, configured to receive coded information and initialize bit information of a variable node; a check node processing circuit, configured to receive first reliability information, and perform check node processing and output second reliability information; a variable node processing circuit, configured to receive the second reliability information, and perform variable node processing to update the bit information of the variable node; a decoding decision circuit, configured to perform a decoding decision for the bit information of the variable node; and a scaling circuit configured to scale the first reliability information transmitted, the second reliability information and the bit information of the variable node.

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives d.sub.c input lists U.sub.i and delivers and delivers d.sub.c output lists V.sub.i, with i[1 . . . d.sub.c]. Each input list and output list includes n.sub.m elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n.sub.m. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of d.sub.c elements of input lists U.sub.i. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A message-passing decoder operates by storing, at a check node, a minimum value, a next-to-minimum value, an edge location of the minimum value, and information regarding the signs of incoming messages. For an edge which is not the location of a previous minimum value, the minimum value and the next-to-minimum value, and the location of the minimum value, are set based on the magnitude of an incoming message. For an edge which is the location of the previous minimum value, the minimum value and the next-to-minimum value are set based on the magnitude of an incoming message, and when the magnitude of the incoming message is at most equal to the previous next-to-minimum value, the location of the minimum value is set to the respective edge, and when the magnitude of the incoming message is greater than the previous next-to-minimum value, the location of the minimum value is approximated.

An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Th.sub.k used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Th.sup.k.sub.i may be calculated for each bit position. Th.sup.k.sub.i and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Th.sub.k used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Th.sup.k.sub.i may be calculated for each bit position. Th.sup.k.sub.i and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of mismatched columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.

A modified version of the min-sum algorithm (MSA) which can lower the error floor performance of quantized LDPC decoders. A threshold attenuated min-sum algorithm (TAMSA) and/or threshold offset min-sum algorithm (TOMSA), which selectively attenuates or offsets a check node log-likelihood ratio (LLR) if the check node receives any variable node LLR with magnitude below a predetermined threshold, while allowing a check node LLR to reach the maximum quantizer level if all the variable node LLRs received by the check node have magnitude greater than the threshold. Embodiments of the present invention can provide desirable results even without knowledge of the location, type, or multiplicity of such objects and can be implemented with only a minor modification to existing decoder hardware.