An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.

An LDPC decoder includes a first circuit is configured to, for a particular check node, determine whether absolute values of two minimums of the absolute values of incoming variable-to-check messages are close to one another. The LDPC decoder includes a second circuit configured to apply either a first scaling value or a second scaling value to check-to-variable messages for the particular check node depending upon whether the first circuit determines that the absolute values of the two minimums of the incoming variable-to-check messages are close to one another.

Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.

A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a 0 or a 1 is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of mismatched columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.

Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

According to an embodiment, a decoding apparatus for a low-density parity-check (LDPC) code includes a first calculator, a second calculator, and a selector. The first calculator is configured to perform row processing based on a first decoding algorithm. The second calculator is configured to perform row processing based on a second decoding algorithm having a lower error correction capacity than that of the first decoding algorithm. The selector is configured to select an output value from the row processing performed by the second calculator when an error in an output value from the row processing performed by the first calculator is greater than an error in the output value from the row processing performed by the second calculator.