Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Th.sub.k used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Th.sup.k.sub.i may be calculated for each bit position. Th.sup.k.sub.i and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Th.sub.k used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Th.sup.k.sub.i may be calculated for each bit position. Th.sup.k.sub.i and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

A message-passing decoder operates by storing, at a check node, a minimum value, a next-to-minimum value, an edge location of the minimum value, and information regarding the signs of incoming messages. For an edge which is not the location of a previous minimum value, the minimum value and the next-to-minimum value, and the location of the minimum value, are set based on the magnitude of an incoming message. For an edge which is the location of the previous minimum value, the minimum value and the next-to-minimum value are set based on the magnitude of an incoming message, and when the magnitude of the incoming message is at most equal to the previous next-to-minimum value, the location of the minimum value is set to the respective edge, and when the magnitude of the incoming message is greater than the previous next-to-minimum value, the location of the minimum value is approximated.

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.

An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z.sub.1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

The invention relates to the field of decoders, more specifically, to a decoding method of LDPC (Low Density Parity Check Code). The decoding method comprising: in the rwsr (Row-Wise Scanning Round) phase, the recovery circuit reads a plurality of sign bits, the absolute value of a minimum value, the absolute value of a second smallest value and the absolute value of a third smallest value which are stored previously, and they are output by a comparison and a selector, the output of the comparator and selector is shifted, and then is combined with each sign bit to obtain an update message of the previous check node, the update message is subtracted from the posterior probability by the addition circuit to obtain an input of the update unit.

Various apparatus and methods may use iterative de-mapping/decoding to on received symbol estimates corresponding to interleaved coded modulation (ICM) using low-density parity check convolutional coding (LPDC-CC). The iterative de-mapping/decoding, may take the form of a multi-stage feed-forward arrangement that may include multiple identically designed stages, and the stages may use parallelism to increase speed and efficiency.