A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.

A method of obtaining a doped semiconductor layer, including the successive steps of: a) performing, in a first single-crystal layer made of a semiconductor alloy of at least a first element A1 and a second element A2, an ion implantation of a first element B which is a dopant for the alloy and of a second element C which is not a dopant for the alloy, to make an upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a doped single-crystal layer of the alloy.

A group III nitride semiconductor substrate may include: a p-type conduction region into which a group II element has been implanted in a depth direction of the group III nitride semiconductor substrate from a surface of the group III nitride semiconductor substrate, the p-type conduction region having p-type conductivity, wherein hydrogen has been implanted from the p-type conduction region across an n-type conduction region adjacent to the p-type conduction region in the depth direction of the group III nitride semiconductor substrate.

A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 110.sup.17 at/cm.sup.3.

There is provided a nitride crystal substrate comprising group-III nitride crystal and containing n-type impurities, wherein an absorption coefficient is approximately expressed by equation (1) in a wavelength range of at least 1 m or more and 3.3 m or less: =n K.sup.a (1) (wherein, (m) is a wavelength, (cm.sup.1) is absorption coefficient of the nitride crystal substrate at 27 C., n (cm.sup.3) is a free electron concentration in the nitride crystal substrate, and K and a are constants, satisfying 1.510.sup.19K6.010.sup.19, a=3).

A technique that recovers from degradation in crystalline nature in an ion-implanted region is provided. A method of manufacturing a semiconductor device, includes: an ion implantation step of ion-implanting p-type impurities by a cumulative dose D into an n-type semiconductor layer containing n-type impurities; and a thermal annealing step of annealing an ion-implanted region of the n-type semiconductor layer where the p-type impurities are ion-implanted, in an atmosphere containing nitrogen, at a temperature T for a time t, wherein the cumulative dose D, the temperature T, and the time t satisfy a predetermined relationship.

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

A method of manufacturing a semiconductor device includes: injecting an inert element or an electron beam into a GaN-based semiconductor substrate; implanting magnesium into the GaN-based semiconductor substrate; and performing a heat treatment after the injecting and the implanting. A first implantation range of inert element or electron beam and a second implantation range of magnesium overlap with each other. A reference depth Dref (nm) calculated using a formula of Dref=D1+140 and a deepest injection depth D1 (nm) in the injecting is deeper than a deepest implantation depth D2 (nm) in the implanting. After the heat treatment, a concentration of magnesium decreases toward a deeper side at a predetermined decrease rate at a position of the reference depth Dref. The predetermined decrease rate is smaller than a decrease rate at which a concentration of magnesium becomes 1/10 per depth of 300 nm.

A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.