Patent classifications
H01L21/30617
Semiconductor Device Gate Spacer Structures and Methods Thereof
A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
Semiconductor Structure and Manufacturing Method for the Semiconductor Structure
Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer.
Stacking fault-free semipolar and nonpolar GaN grown on foreign substrates by eliminating the nitrogen polar facets during the growth
Methods and structures for forming epitaxial layers of Ill-nitride materials on patterned foreign substrates with low stacking fault densities are described. Semipolar and nonpolar orientations of GaN that are essentially free from stacking faults may be grown from crystal-growth facets of a patterned substrate. Etching can be used to remove stacking faults if present. Crystal growth with an impurity can eliminate crystal growth from a facet that is responsible for stacking fault formation and permit substantially stacking-fault-free growth of the Ill-nitride material.
Semiconductor device having metallic source and drain regions
Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
Self-aligned tunneling field effect transistors
Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.
Semiconductor device gate spacer structures and methods thereof
A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
ETCHING SOLUTION, ADDITIVE, AND ETCHING METHOD
According to one embodiment, an etching solution is provided. The etching solution is used for etching of silicon nitride. The etching solution includes: phosphoric acid; tetrafluoroboric acid; a silicon compound; water; and at least one of sulfuric acid and an ionic liquid.
Growing Groups III-V lateral nanowire channels
In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.
Method for recovering carbon-face-polarized silicon carbide substrate
A method for recovering carbon-face-polarized silicon carbide substrates, including: providing an epitaxial structure, the epitaxial structure includes a carbon-face-polarized silicon carbide substrate to be recovered, as well as a nitrogen-face-polarized gallium nitride buffer layer, a barrier layer and a nitrogen-face-polarized gallium nitride channel layer that are sequentially deposited on the silicon carbide substrate; removing the nitrogen-face-polarized gallium nitride buffer layer, the barrier layer and the nitrogen-face-polarized gallium nitride channel layer by wet etching; and cleaning and blowing dry the carbon-face-polarized silicon carbide substrate.