A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.

A method of forming a nanosheet semiconductor device that includes epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first III-V semiconductor material and a second nanosheet layer of a second III-V semiconductor material. A sacrificial gate structure is formed on the stack of the at least two repeating nanosheets. Source and drain regions are epitaxially formed on the second nanosheet layer. The sacrificial gate structure is removed to provide a gate opening. An etch process removes the first nanosheet layer selectively to the second nanosheet layer, wherein the etch process is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack. A dielectric layer is deposited filling the inverted apex. A functional gate structure is formed in the gate opening.

Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. Charge carriers are driven away from the surface of the semiconductor on a timescale short compared to the carrier recombination lifetime. Such methods are applied to creating a spatially varying doping profile in the semiconductor substrate, a photonic integrated circuit and an integrated photonic microfluidic circuit.

Methods and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g., via atomic layer deposition) a continuous film of a protection material (e.g., Al.sub.2O.sub.3) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.

A method of processing a workpiece includes: a frame unit preparing step of preparing a frame unit including a tape affixed to an undersurface of the workpiece; a protective film forming step of forming a protective film on a top surface of the workpiece; a cutting step of cutting the workpiece by applying a laser beam; an interval expanding step of widening intervals between chips formed in the cutting step by expanding the tape outward in a radial direction; and an etching step of removing altered regions formed in the respective chips.

A method of manufacturing a patterned aluminum nitride layer includes growing an amorphous patterned layer on a seed layer, which promotes growth of a first type aluminum nitride layer that has a disordered crystallographic structure. The seed layer promotes growth of a second type aluminum nitride layer with a vertically oriented columnar crystal structure. The method also includes depositing an aluminum nitride layer over the amorphous patterned layer and the seed layer to form the first type aluminum nitride layer with the disordered crystallographic structure over the amorphous patterned layer and the second type aluminum nitride layer with the vertically oriented columnar crystal structure over the seed layer. The method also includes depositing a masking layer over the second type aluminum nitride layer and etching away the first type aluminum nitride layer.

A method comprises providing a substrate comprising an n-type Al/In/GaN semiconductor material. A surface of the substrate is dry-etched to form a trench therein and cause dry-etch damage to remain on the surface. The surface of the substrate is immersed in an electrolyte solution and illuminated with above bandgap light having a wavelength that generates electron-hole pairs in the n-type Al/In/GaN semiconductor material, thereby photoelectrochemically etching the surface to remove at least a portion of the dry-etch damage.

Methods and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g., via atomic layer deposition) a continuous film of a protection material (e.g., Al.sub.2O.sub.3) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.

Systems, methods and instrumentalities are disclosed for uplink beam management. A wireless transmit/receive unit (WTRU) may send a beam correspondence indication to a network device. The beam correspondence indication may indicate a beam correspondence associated with one or more receive beams and one or more transmit beams of the WTRU. The WTRU may determine an uplink time synchronization status associated with the WTRU. The uplink time synchronization status may indicate whether the WTRU is uplink time synchronized. The WTRU may receive, from the network device, a reference signal type in accordance with the determined uplink time synchronization status. The WTRU may receive, from the network device, a beam management indication in response to the beam correspondence indication. The WTRU may perform an uplink beam management based on the received beam management indication.

Semiconductor devices and methods of forming the same include forming a doped drain structure having a first conductivity type on sidewalls of an intrinsic channel layer. An opening is etched in a middle of the channel layer. A doped source structure is formed having a second conductivity type in the opening of the channel layer.