The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

A plasma processing apparatus includes a chamber; a substrate support disposed in the chamber and including a lower electrode; an upper electrode disposed above the substrate support; an RF source that supplies an RF power to the lower electrode or the upper electrode, the RF power having a plurality of power levels during a first sequence in a repeating time period, the plurality of power levels including a first power level during a first state and a second state, and a second power level during a third state and a fourth state; and a DC source that applies a DC voltage to the lower electrode, the DC voltage having a plurality of voltage levels during the first sequence in the repeating time period.

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

A substrate processing method processes a substrate which has a metal layer on a principal surface. The substrate processing method includes a metal oxide layer forming step in which an oxidizing fluid is supplied toward the principal surface of the substrate, thereby forming a metal oxide layer constituted of one atomic layer or several atomic layers on a surface layer of the metal layer and a metal oxide layer removing step in which an etching fluid containing at least one of water in a gaseous state and water in a mist state as well as a reactive gas that reacts with the metal oxide layer together with the water is supplied toward the principal surface of the substrate, thereby etching the metal oxide layer and selectively removing it from the substrate. Then, cycle processing in which the metal oxide layer forming step and the metal oxide layer removing step are given as one cycle is executed at least in one cycle, thereby controlling the etching amount of the metal layer for each cycle at an accuracy of a nanometer or less.

An apparatus and methods for selectively etching a particular layer are disclosed. The apparatus and methods are directed towards maintaining the etch rate of the particular layer, while keeping intact a non-etched layer. A gas mixture may be flowed onto the substrate in separate loops having an oxide layer and an oxynitride layer as an etch layer and a nitride layer as a non-etched layer, for example. A reaction between the resulting gas mixture and the particular layer takes place, resulting in etching of the oxide layer and the oxynitride layer while maintaining the nitride layer in the above example.

Methods for evaluating synergy of modification and removal operations for a wide variety of materials to determine process conditions for self-limiting etching by atomic layer etching are provided herein. Methods include determining the surface binding energy of the material, selecting a modification gas for the material where process conditions for modifying a surface of the material generate energy less than the modification energy and greater than the desorption energy, selecting a removal gas where process conditions for removing the modified surface generate energy greater than the desorption energy to remove the modified surface but less than the surface binding energy of the material to prevent sputtering, and calculating synergy to maximize the process window for atomic layer etching.

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

A method for controlling an electrostatic attractor, which attracts an electrode to a gas plate provided in an upper portion of a plasma processing apparatus, includes, among a plasma generation period in which plasma is generated by the plasma processing apparatus and an idle period in which no plasma is generated by the plasma processing apparatus, applying voltages having polarities different from each other to first and second electrodes of the electrostatic attractor in at least the idle period.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.