The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate; forming at least one sacrificial layer and at least one liner layer, that are alternately stacked over each other, on the substrate; etching the at least one liner layer and the at least one sacrificial layer until the substrate is exposed, to form a plurality of fins, discretely arranged on the substrate; and etching a portion of a thickness of the substrate, such that a width of the etched portion of the substrate at a bottom of the at least one sacrificial layer is less than a width of the at least one liner layer of the plurality of fins.

A semiconductor device includes a first layer that contains gold (Au) and is formed on one surface of a semiconductor substrate and a second layer that contains nickel (Ni) and is formed on the first layer. The semiconductor device is provided with a via hole that passes through the second layer, the first layer, and the semiconductor substrate from one surface to another surface opposite thereto, and a via wiring is formed on the inner surface of the via hole. The second layer is a mask used when the semiconductor substrate is etched to form the via hole, and the first layer is a base layer for forming the second layer on the semiconductor substrate. By using an Au-containing layer as the first layer, side etching on the first layer is prevented when the semiconductor substrate is etched, and disconnection of the via wiring is prevented.

Methods and apparatus for processing a photonic device are provided herein. For example, methods include etching, using a plasma etch process that uses a first gas, a first epitaxial layer of material of the photonic device comprising a base layer comprising at least one of silicon, germanium, sapphire, aluminum indium gallium arsenide (Al.sub.xIn.sub.yGa.sub.1-x-yAs), aluminum indium gallium phosphide (Al.sub.xIn.sub.yGa.sub.1-x-yP), aluminum indium gallium nitride (Al.sub.xIn.sub.yGa.sub.1-x-yN), aluminum indium gallium arsenide phosphide (Al.sub.xIn.sub.yGa.sub.1-x-yAs.sub.zP.sub.1-z), depositing, using a plasma deposition process that uses a second gas different from the first gas, a first dielectric layer over etched sidewalls of the first epitaxial layer of material, etching, using the first gas, a second epitaxial layer of material of the photonic device, and depositing, using the second gas, a second dielectric layer over etched sidewalls of the second epitaxial layer of material.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

A method for manufacturing a semiconductor substrate having a patterned group-III nitride compound layer without collapsing a formed mask pattern due to reflow or decomposition even when an etching method at a high temperature of 300° C.-700° C. is used, including the steps: forming a patterned mask layer on the substrate's group-III nitride compound layer, and etching the group-III nitride compound layer by dry etching at 300° C. or higher and 700° C. or lower using the mask pattern, to form patterned group-III nitride compound layer, wherein the patterned mask layer contains a polymer containing a unit structure of the following Formula (1): ##STR00001##
a polymer containing a unit structure of the following Formula (2):
O—Ar.sub.1  Formula (2)
a polymer containing a structural unit of the following Formula (3):
O—Ar.sub.2—O—Ar.sub.3-T-Ar.sub.4  Formula (3)
a polymer containing a combination of unit structure of Formula (2) and unit structure of Formula (3), or a crosslinked structure of the polymers.

The present invention discloses a precise etching apparatus for preparing a recessed-gate enhancement device and an etching method for the same. The apparatus provided by the present invention includes an inductively-coupled plasma etching chamber, a current detection device, an inductive coil, a radio frequency source, a mechanical pump, and a molecular pump. The current detection device is connected with the inductively-coupled plasma etching chamber. The inductive coil is connected with the inductively-coupled plasma etching chamber. The radio frequency source is connected with the inductive coil. The mechanical pump and the molecular pump are connected with the inductively-coupled plasma etching chamber. When a displayed current value is zero during an HEMT device preparation process, the apparatus shuts off a two-dimensional electron gas channel, and etching is terminated, thereby preventing gate leakage caused by over-etching or damage to the two-dimensional electron gas channel, thus achieving precise etching.

A method of polishing a semiconductor substrate, including: a) a step of multiple implantations of ions from an upper surface of the substrate, to modify the material of an upper portion of the substrate, the multiple implantation step comprising a plurality of successive implantations under different respective implantation orientations; and b) a step of selective removal of the upper portion of the substrate.

A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.