A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multi-layer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.

The present disclosure provides a manufacturing method of a display substrate, a display substrate and a display device, belongs to the field of display technology, and can at least partially solve a problem of residual sand in the display substrate. The manufacturing method of the display substrate includes: providing a base; forming a passivation layer on a surface of the base; forming an amorphous oxide conductive material layer on a surface of the passivation layer facing away from the base; forming a photoresist pattern on the oxide conductive material layer, the photoresist pattern having an exposure region; etching a portion of the oxide conductive material layer in the exposure region of the photoresist pattern to form a hollow position exposing a portion of the passivation layer; and removing a certain thickness material of the portion of the passivation layer exposed through the hollow position.

A method of manufacturing a semiconductor device may include forming a first stack structure by alternately stacking first material layers and second material layers, forming first holes penetrating the first stack structure and a first slit located between the first holes, forming channel patterns in the first holes and a dummy channel pattern in the first slit, selectively removing the dummy channel pattern from the first slit, and replacing the first material layers with third material layers through the first slit.

A method for fabricating silicon nanostructures. An etch uniformity improving layer is deposited on a substrate. A catalyst (e.g., thin film of Ti/Au) is deposited on the substrate or the etch uniformity improving layer, where the catalyst is contacting a portion of the substrate or the etch uniformity layer. The catalyst and the substrate or etch uniformity improving layer are exposed to an etchant, where the catalyst causes etching of the substrate thereby creating etched nanostructures.

A channel structure includes a first patterned channel layer including a lower portion and an upper portion. The upper portion is disposed on the lower portion. A width of the upper portion is larger than a width of the lower portion. A material or a material composition ratio of the upper portion is different from a material or a material composition ratio of the lower portion. The height and the channel length of the channel structure are increased by disposing the first patterned channel layer, and the saturation current (I.sub.sat) of a transistor including the channel structure of the present invention may be enhanced accordingly.

The present disclosure provides methods of forming semiconductor devices. A method according to the present disclosure includes receiving a workpiece that includes a stack of semiconductor layers, depositing a first pad oxide layer on a germanium-containing top layer of the stack, depositing a second pad oxide layer on the first pad oxide layer, depositing a pad nitride layer on the second pad oxide layer, and patterning the stack using the first pad oxide layer, the second pad oxide layer, and the pad nitride layer as a hard mask layer. The depositing of the first pad oxide layer includes a first oxygen plasma power and the depositing of the second pad oxide layer includes a second oxygen plasma power greater than the first oxygen plasma power.

Disclosed and claimed herein is a composition for forming a spin-on hard-mask, having a fullerene derivative and a crosslinking agent. Further disclosed is a process for forming a hard-mask.

Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.