A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate structures are disposed on a substrate. The epitaxial structure is disposed in the substrate between the gate structures, wherein a protruding portion of the substrate extends into the epitaxial structure in a protection direction.

A method of concurrently etching a first region in which silicon oxide films and silicon nitride films are alternately stacked and a second region including the silicon oxide film having a thickness larger than a thickness of the silicon oxide film of the first region is provided. The method includes generating plasma of a first processing gas containing a fluorocarbon gas and a hydrofluorocarbon gas within a processing vessel of a plasma processing apparatus into which a processing target object is carried; and generating plasma of a second processing gas containing a hydrogen gas, a hydrofluorocarbon gas and a nitrogen gas within the processing vessel of the plasma processing apparatus. Further, the generating of the plasma of the first processing gas and the generating of the plasma of the second processing gas are repeated alternately.

Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.

An annular member is disposed to surround a pedestal for receiving a substrate in a plasma processing apparatus. The annular member contains quartz and silicon. A content percentage of the silicon in the quartz and the silicon is 2.5% or more and 10% and less by weight.

A method for patterning a substrate including multiple layers using a sulfur-based mask includes providing a substrate including a first layer and a second layer arranged on the first layer. The first layer includes a material selected from a group consisting of germanium, silicon germanium and type III/V materials. The method includes depositing a mask layer including sulfur species on sidewalls of the first layer and the second layer by exposing the substrate to a first wet chemistry. The method includes removing the mask layer on the sidewalls of the second layer while not completely removing the mask layer on the sidewalls of the first layer by exposing the substrate to a second wet chemistry. The method includes selectively etching the second layer relative to the first layer and the mask layer on the sidewalls of the first layer by exposing the substrate to a third wet chemistry.

An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n.sup.+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

Disclosed is a method for etching a first region including a multi-layer film formed by providing silicon oxide films and silicon nitride films alternately, and a second region having a single silicon oxide film. The etching method includes: providing a processing target object including a mask provided on the first region and the second region within a processing container of a plasma processing apparatus; generating plasma of a first processing gas including a hydrofluorocarbon gas within the processing container that accommodates the processing target object; and generating plasma of a second processing gas including a fluorocarbon gas within the processing container that accommodates the processing target object. The step of generating the plasma of the first processing gas and the step of generating the plasma of the second processing gas are alternately repeated.

The present description relates to a gallium nitride transistor which includes at least one source/drain structure having low contact resistance between a 2D electron gas of the gallium nitride transistor and the source/drain structure. The low contact resistance may be a result of at least a portion of the source/drain structure being a single-crystal structure abutting the 2D electron gas. In one embodiment, the single-crystal structure is grown with a portion of a charge inducing layer of the gallium nitride transistor acting as a nucleation site.

One illustrative method disclosed herein includes, among other things, forming an original fin-formation etch mask comprised of a plurality of original line-type features and removing at least a portion of at least one of the plurality of original line-type features so as to thereby define a modified fin-formation etch mask comprising the remaining portions of the plurality of original line-type features. The method also includes forming a conformal layer of material on the remaining portions of the plurality of original line-type features of the modified fin-formation etch mask and performing at least one etching process to remove at least portions of the conformal layer of material and to define a plurality of fin-formation trenches so as to thereby initially define a plurality of fins in the substrate.

An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.