A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

Provided is a kit including a curable composition for imprinting, and a composition for forming an underlayer film for imprinting, in which the composition for forming an underlayer film for imprinting contains a polymer having a polymerizable functional group, and a compound in which the lower one of a boiling point and a thermal decomposition temperature is 480° C. or higher and ΔHSP, which is a Hansen solubility parameter distance from a component with the highest content contained in the curable composition for imprinting, is 2.5 or less. Furthermore, the present invention relates to a composition for forming an underlayer film for imprinting, a pattern forming method, and a method for manufacturing a semiconductor device, which are related to the kit.

A method for adjusting wafer deformation and a semiconductor structure are provided. The method includes the following operations. A deformation position and a deformation degree of a wafer are determined. At least one groove is formed at a back of the wafer according to the deformation position and the deformation degree. A stress film having a stress effect on the wafer deformation is formed at the back of the wafer with the at least one groove, and the stress film covers an inner wall of the at least one groove.

A radiation sensitive composition including a siloxane polymer exhibiting phenoplast crosslinking reactivity as a base resin, which is excellent in resolution and can be used as a radiation sensitive composition capable of allowing a pattern having a desired-shape to be formed with sufficient precision. A radiation sensitive composition including as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof; and a photoacid generator, in which the hydrolyzable silane includes hydrolyzable silanes of Formula (1)
R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4-(a+b)  Formula (1)
wherein R.sup.1 is an organic group of Formula (1-2) ##STR00001##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.3 is a hydrolyzable group; and Formula (2)
R.sup.7.sub.cR.sup.8.sub.dSi(R.sup.9).sub.4-(c+d)  Formula (2)
wherein R.sup.7 is an organic group of Formula (2-1) ##STR00002##
and is bonded to a silicon atom through a Si—C bond or a Si—O bond, and R.sup.9 is a hydrolyzable group.

The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

The present disclosure relates to a patterning method and a method of manufacturing a semiconductor structure. The patterning method includes: providing a base; forming a first patterned mask layer on a surface of the base, where the first patterned mask layer includes a plurality of first mask structures extending along a first direction, and the first mask structures are arranged at intervals; forming a first dielectric layer on the first patterned mask layer, where the first dielectric layer fills up a spacing region between the first mask structures and covers an upper surface of the first patterned mask layer; and etching the first dielectric layer to form a plurality of second mask structures extending along a second direction, where the second mask structures are arranged at intervals, and the second direction intersects with the first direction; and selectively etching the first mask structure and the second mask structure.

Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.

A method of forming alignment marks, each alignment mark including a plurality of fiducials, includes providing a III-V compound substrate having a device region and an alignment mark region. The method also includes forming a first hardmask in the device region and a hardmask structure in the alignment mark region, etching a first surface portion of the III-V compound substrate to form a plurality of trenches in the device region, and epitaxially regrowing a semiconductor layer in the trenches. The method further includes forming a second mask in the device region and a patterned structure in the alignment mark region. The patterned structure includes a set of masked regions corresponding to the plurality of fiducials and a second set of openings. The method also includes forming the plurality of fiducials.

A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.

A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.