A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.

A method of manufacturing a semiconductor device includes providing a lower structure, sequentially forming a dielectric layer and a mask layer having a first intermediate opening on the lower structure, forming a first opening extending in a first direction to at least partially overlap the first intermediate opening, in the mask layer, forming a spacer layer on a sidewall of the mask layer to be positioned in a portion of each of the first intermediate opening and the first opening, forming second openings spaced apart by the first intermediate opening in the first direction, in the mask layer, patterning the dielectric layer using the mask layer, and forming a metal material layer by filling a patterned region of the dielectric layer with a metal material.

A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

The present disclosure provides a manufacturing method for semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate; forming first mask patterns and first mask openings on the substrate, the first mask opening being located between the adjacent first mask patterns; forming second mask patterns and second mask openings on the first mask patterns and the first mask openings, the second mask opening being located between the adjacent second mask patterns; and forming first patterns and first openings on the substrate based on the first mask patterns, the first mask openings, the second mask patterns and the second mask openings.

The present techniques relate to various aspects of forming and filling high-aspect ratio trench structures (e.g., trench structures having an aspect ratio of 20 or greater, including aspect ratios in the range of 20:1 up to and including 50:1 or greater) combined with trench opening widths ranging from 0.5 micron to 50 microns. In one implementation a method to fabricate high-aspect ratio trenches in silicon is provided using a patterned photoresist on evaporated aluminum. In accordance with this approach, a high-aspect ratio trench can be formed having vertical side walls and defect-free trench bottoms. In some instances it may be desirable to fill such high-aspect ratio trench structures with a metal or other substrate to provide certain functionality associated with the fill material. Further processes and structures are related in which such trench structures are filled using a mixture of high-Z nano-particles within an epoxy resin matrix.

A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view . Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each of the discrete sacrificial layers. Each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the discrete sacrificial layers. The method further includes: removing the first top region of each first initial spacer to form a first spacer from each first bottom region; forming second spacers on sidewalls of each of the first spacers. Each second spacer includes a second bottom region and a second top region on the second bottom region; removing the first spacers; The method further includes: removing the second top regions by etching; and etching the to-be-etched material layer by using the second spacers as a mask.

A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.