The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method includes forming an etching stop layer on a substrate, forming a target layer on the etching stop layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers.

A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns. In embodiments and implementations of this application, the filling layer is formed between the mask layers of the second region, to obtain a mask that finally etches the pattern definition layer, so that the formed target patterns meet process requirements, which is conducive to improving electrical performance of the semiconductor structure.

The present application discloses a method for fabricating a semiconductor device using a tilted etch process. The method includes forming an etching stop layer on a substrate, forming a target layer on the etching stop layer, forming a first hard mask layer on the target layer, forming second hard mask layers on the first hard mask layer, performing a first tilted etch process on the first hard mask layer to form first openings along the first hard mask layer and adjacent to first sides of the second hard mask layers, and performing a second tilted etch process on the first hard mask layer to form second openings along the first hard mask layer and adjacent to second sides of the second hard mask layers.

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a substrate having a first region, second regions and third regions; and forming a patterned structure on the substrate. The patterned structure includes at least one first patterned layer on the first region, at least one second patterned layer on the second region and at least one third patterned layer on the third region, the at least one first patterned layer is discrete from the at least one second region and the at least one second region is discrete from the at least one third region. The method also includes removing the second patterned layer; and etching the substrate using the first patterned layer and the third patterned layer as an etching mask to form a base substrate, the first fin on the base substrate and the third fin on the base substrate.

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.

The present invention is a composition for forming a silicon-containing metal hard mask, including: (A) a metal oxide nanoparticle; (B) a thermally crosslinkable polysiloxane (Sx) having no aromatic-ring-containing organic group; and (C) a solvent. This provides a composition for forming a silicon-containing metal hard mask that has a high effect of inhibiting collapse of an ultrafine pattern in a multilayer resist method, that can form a resist pattern having excellent LWR, that has more excellent dry etching resistance and wet removability than a conventional silicon-containing underlayer film material, and that has more excellent filling ability than a conventional metal hard mask material.

A carrier proximity mask and methods of assembling and using the carrier proximity mask may include providing a first carrier body, second carrier body, and set of one or more clamps. The first carrier body may have one or more openings formed as proximity masks to form structures on a first side of a substrate. The first and second carrier bodies may have one or more contact areas to align with one or more contact areas on a first and second sides of the substrate. The set of one or more clamps may clamp the substrate between the first carrier body and the second carrier body at contact areas to suspend work areas of the substrate between the first and second carrier bodies. The openings to define edges to convolve beams to form structures on the substrate.

Methods, systems, and computer programs are presented for selective deposition of etch-stop layers for enhanced patterning during semiconductor manufacturing. One method includes an operation for adding a photo-resist material (M2) on top of a base material (M1) of a substrate, M2 defining a pattern for etching M1 in areas where M2 is not present above M1. The method further includes operations for conformally capping the substrate with an oxide material (M3) after adding M2, and for gap tilling the substrate with filling material M4 after the conformally capping. Further, a stop-etch material (M5) is selectively grown on exposed surfaces of M3 and not on surfaces of M4 after the gap filling. Additionally, the method includes operations for removing M4 from the substrate after selectively growing M5, and for etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etching protection to enable deeper etching into M1.

Methods and systems for etching SiCN with mutli-color selectivity may include receiving the substrate having a multi-line layer formed thereon, the multi-line layer including a region having a pattern of alternating lines of a plurality of materials, wherein each line has a horizontal thickness, a vertical height, and extends horizontally across an underlying layer, wherein each line of the pattern of alternating lines extends vertically from a top surface of the multi-line layer to a bottom surface of the multi-line layer. Such a method may also include forming a patterned recess in the multi-line layer to expose at least a first component of the multi-line layer and a second component of the multi-line layer. An embodiment of a method many also include etching the first component with a non-corrosive etch process that is selective to the second component.