A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.

The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench defined by sidewalls of the substrate that surround the source region and the drain region. The one or more dielectric materials include one or more interior surfaces defining a recess within the one or more dielectric materials. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate material over the upper surface of the substrate and a second gate material. The second gate material completely fills the recess as viewed along a cross-sectional view.

Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.

The present application discloses a semiconductor device with an inverter and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure positioned on the substrate; a first impurity region and a second impurity region respectively positioned on two sides of the gate structure and positioned in the substrate; a first contact positioned on the first impurity region and including a first resistance; a second contact positioned on the first impurity region and including a second resistance less than the first resistance of the first contact. The first contact is configured to electrically couple to a power supply and the second contact is configured to electrically couple to a signal output. The gate structure, the first impurity region, the second impurity region, the first contact, and the second contact together configure an inverter.

An IC includes a first and second active areas (AA) with a second conductivity type, a source and drain region, and an LDD extension to the source and drain in the first AA having a first conductivity type. A first bent-gate transistor includes a first gate electrode over the first AA extending over the corresponding LDD. The first gate electrode includes an angled portion that crosses the first AA at an angle of 45° to 80°. A second transistor includes a second gate electrode over the second AA extending over the corresponding LDD including a second gate electrode that can cross an edge of the second AA at an angle of about 90°. A first pocket distribution of the second conductivity type provides a pocket region under the first gate electrode. A threshold voltage of the first bent-gate transistor is ≥30 mV lower as compared to the second transistor.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.