A semiconductor device of an embodiment includes: a first and second semiconductor regions of a first conductivity type; a third semiconductor region of a second conductivity type disposed between the first and second semiconductor regions; a fourth semiconductor region of the first conductivity type disposed below the first semiconductor region; a fifth semiconductor region of the first conductivity type disposed below the second semiconductor region; a first region containing carbon disposed between the first and fourth semiconductor regions; a second region containing carbon disposed between the second and fifth semiconductor regions; a third region disposed between the first and second regions; the first and second regions having a first and second carbon concentrations respectively, the third region not containing carbon or having a lower carbon concentration than the first and second carbon concentrations in a portion below an end of a lower face of a gate electrode.

A transistor structure includes a gate conductive region, a gate dielectric region, a channel region and a drain region. The gate conductive region is below an original surface of a substrate. The gate dielectric region surrounds the gate conductive region. The channel region surrounds the gate dielectric region. The drain region is horizontally spaced apart from the gate conductive region, wherein the drain region includes a highly doped region; wherein the gate dielectric region includes a first dielectric portion and a second dielectric portion, the first dielectric portion is positioned between the gate conductive region and the highly doped region, and the second dielectric portion is positioned between the gate conductive region and the channel region; wherein a horizontal thickness of the first dielectric portion is greater than that of the second dielectric portion.

A method for manufacturing a semiconductor product is provided. The method comprises forming a semiconductor device within a wafer utilizing a predetermined number of masks. The method further comprises forming a first low-leakage semiconductor device within the wafer utilizing a first set of additional masks. The first low-leakage semiconductor device has a lower leakage current than that of the semiconductor device.

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

A method for forming an integrated circuit structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; forming a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, in which the dielectric layer has a first portion alongside a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode alongside the first portion of the dielectric layer; and forming source/drain features in the semiconductor substrate.

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.

A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.

A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.