A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.

A self-aligning preparation method for a drain underlap region in a tunnel field effect transistor: designing asymmetric side wall structures on two sides of the gate of a tunnel field effect transistor, the side of the gate closest to the source region being a thin side wall and the side of the gate closest to the drain region being a thick side wall; and using the source region thin side wall as a hard mask for implantation of the source region of the transistor and the drain region thick side wall as a hard mask for implantation of the drain region of the transistor. The present method effectively uses the thin side walls and thick side walls existing in standard CMOS processes to suppress the ambipolar effect of the tunnel field effect transistor without introducing special materials and special processes, and also optimizes the device variation characteristics. The present method ensures that the tunnel field effect transistor can be monolithically integrated with standard CMOS devices to implement more complex and diverse circuit functions.

A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

A first field effect transistor contains a first active region including a source region, a drain region and a channel region located between the source region and the drain region, a first gate dielectric overlying the active region, and a first gate electrode overlying the first gate dielectric. A second field effect transistor contains a second active region including a source region, a drain region and a channel region located between the source region and the drain region, a second gate dielectric overlying the active region, a second gate electrode overlying the second gate dielectric. A trench isolation region surrounds the first and the second active regions. The first field effect transistor includes a fringe region in which the first gate electrode extends past the active region perpendicular to the source region to drain region direction and the second field effect transistor does not include the fringe region.

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.