A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.

A shield trench power device such as a trench MOSFET or IGBT employs a gate structure with an underlying polysilicon shield region overlying a shield region in an epitaxial or crystalline layer of the device. The polysilicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

A semiconductor device is described. The semiconductor device includes: a Si substrate having a first main surface; a plurality of gate trenches extending from the first main surface into the Si substrate; a semiconductor mesa between adjacent gate trenches; a first interlayer dielectric on the first main surface; a plurality of first metal contacts extending through the first interlayer dielectric and contacting gate electrodes disposed in the gate trenches; a plurality of second metal contacts extending through the first interlayer dielectric and contacting the semiconductor mesas; and an air gap or a dielectric material having a lower dielectric constant than the first interlayer dielectric between adjacent first and second metal contacts. Methods of producing the semiconductor device are also described.

An embodiment relates to a method for manufacturing a semiconductor device. The method includes providing a semiconductor body including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type interposed between the first semiconductor region and a first surface of the semiconductor body. The method further includes forming a first contact layer over the first surface of the semiconductor body. The first contact layer forms a direct electrical contact to the second semiconductor region. The method further includes forming a contact trench extending into the semiconductor body by removing at least a portion of the second semiconductor region. The method further includes forming a second contact layer in the contact trench. The second contact layer is directly electrically connected to the semiconductor body at a bottom side of the contact trench.

A split gate MOSFET is provided. The split gate MOSFET may have a low capacitance between a gate electrode and a source electrode. The trench MOSFET includes a substrate; a gate trench formed on the substrate; a sidewall insulating layer formed on a sidewall of the gate trench; a source electrode surrounded by the sidewall insulating layer; a first upper electrode provided above the source electrode; a first inter-electrode insulating layer formed between the source electrode and the first upper electrode; a second upper electrode formed adjacent to a side of the first upper electrode and surrounding the first upper electrode; and an interlayer insulating layer formed on the first upper electrode and the second upper electrode.

A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.

A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

A wide band gap semiconductor device includes a semiconductor layer, a trench formed in the semiconductor layer, first, second, and third regions having particular conductivity types and defining sides of the trench, and a first electrode embedded inside an insulating film in the trench. The second region integrally includes a first portion arranged closer to a first surface of the semiconductor layer than to a bottom surface of the trench, and a second portion projecting from the first portion toward a second surface of the semiconductor layer to a depth below a bottom surface of the trench. The second portion of the second region defines a boundary surface with the third region, the boundary region being at an incline with respect to the first surface of the semiconductor layer.

The present disclosure relates to a method for manufacturing a trench-gate MOSFET. In the method, a first trench is formed in a first region and a second trench is formed in a second region in an epitaxial layer. A first well is formed in a bottom surface of the first trench in the first region, and a body region is formed in the epitaxial layer in the second region, simultaneously in one ion implantation process with one mask being used. Thus, the method reduces a number of masks and simplifies ion implantation processes, thereby reducing manufacturing cost.