To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.

A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. A trench is formed through the semiconductor layer. An insulating material is disposed in the trench. A first column of semiconductor material having a first conductivity type extends through the semiconductor layer adjacent to the trench. A second column of semiconductor material having a second conductivity type extends through the semiconductor layer adjacent to the first column of semiconductor material. A first insulating layer is formed between the insulating material and a side surface of the trench. A source region is formed within the semiconductor layer. A gate region is formed adjacent to the insulating layer. A second insulating layer is formed between the gate region and source region. A conductive layer is formed over the semiconductor layer. The source region is coupled to the conductive layer.

A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on the second electrode portion, the first electrode portion being provided between the first trench and the second trench, the first electrode portion reaching the first semiconductor region from above the second semiconductor region, the first electrode portion being electrically connected to the first semiconductor region and the second semiconductor region; a third semiconductor region provided between the third electrode and the second semiconductor region provided between the first insulating film and the third electrode, the third semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; a fourth semiconductor region provided between the third electrode and the second semiconductor region provided between the second insulating film and the third electrode, the fourth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; and a fifth semiconductor region provided between the first semiconductor region and the third electrode, the fifth semiconductor region being provided apart from the third semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region.

A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Disclosed is a split-gate MOSFET and a manufacturing method, comprising: forming a cavity in a semiconductor layer; form a first trench based on the cavity; forming a second trench communicated with the first trench and extending in a same direction with the second trench; forming a first dielectric layer and a second dielectric layer; forming a first conductor located in the second trench and isolated from the semiconductor layer by the first dielectric layer; forming a third dielectric layer covering a surface of the first conductor; forming a second conductor located in the first trench, isolated from the semiconductor layer by the second dielectric layer, and isolated from the second conductor by the third dielectric layer; forming a body region adjacent to the first trench, wherein an inner diameter of the first trench is larger than an inner diameter of the second trench. The manufacturing method expands a process window.

Disclosed is a split-gate MOSFET and a manufacturing method, including: forming a first trench in a semiconductor layer; forming a second trench communicated with the first trench by using the first trench; forming a first dielectric layer in the second trench, a second dielectric layer in the first trench; forming a first conductor, located in the second trench, isolated from the semiconductor layer by the first dielectric layer; forming a third dielectric layer covering the first conductor; forming a second conductor, located in the first trench, isolated from the semiconductor layer by the second dielectric layer, the first conductor being isolated from the second conductor by the third dielectric layer; forming a body region adjacent to the first trench, the first trench has an inner diameter greater than that of the second trench. Thus, process window is expanded and beneficial to forming the third dielectric layer.

What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.