A thin film transistor includes an active layer, first and second electrodes, and a third doped pattern. The active layer has a channel region, and a first electrode region and a second electrode region, the first electrode region has a first ion doping concentration, and the second electrode region has a second ion doping concentration. The first electrode and the second electrode are disposed on a side of the active layer in the thickness direction. The first electrode is coupled to the first electrode region, and the second electrode is coupled to the second electrode region. The third doped pattern is disposed between the first electrode and the first electrode region, and in direct contact with the first electrode and the first electrode region. The third doped pattern has a third ion doping concentration, and the third ion doping concentration is different from the first ion doping concentration.

A display device includes an organic light emitting diode, a first transistor driving the organic light emitting diode, a second transistor transmitting a data signal to the first transistor, a third transistor transmitting a first power voltage to the first transistor, wherein a semiconductor pattern of the first transistor is disposed over a semiconductor pattern of the second transistor, a semiconductor pattern of the third transistor is disposed over the semiconductor pattern of the first transistor, a lower transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, and an upper transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.

A thin film transistor includes a substrate and an active layer having a channel region. The active layer includes a first active pattern and at least one second active pattern. The first active pattern includes a bottom surface, a top surface and at least one side surface. The at least one side surface connects the bottom and top surfaces, and is in contact with the at least one second active pattern. A length direction of each side surface is approximately perpendicular to a length direction of the channel region. A material of at least the top surface of the first active pattern includes a first polysilicon material, and a material of the second active pattern includes a second polysilicon material; and in the length direction of the channel region, an average grain size of the first polysilicon material is greater than an average grain size of the second polysilicon material.

A thin film transistor is provided. The thin film transistor includes abase substrate; a gate electrode on the base substrate; an active layer on the base substrate, the active layer including a polycrystalline silicon part including a polycrystalline silicon material and an amorphous silicon part including an amorphous silicon material; a gate insulating layer insulating the gate electrode from the active layer; a source electrode and a drain electrode on the base substrate; and an etch stop layer on a side of the polycrystalline silicon part away from the base substrate. An orthographic projection of the etch stop layer on the base substrate covers an orthographic projection of the polycrystalline silicon part on the base substrate, and an orthographic projection of at least a portion of the amorphous silicon part on the base substrate.

A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.

Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

Provided are an array substrate and a fabrication method therefor, a shift register unit, and a display panel. The array substrate includes a first transistor having a double gate structure, and further includes an active layer arranged on one side of the base substrate and a first conductive layer. The active layer includes a first conductor portion connected between a first semiconductor portion and a second semiconductor portion, the first semiconductor portion and a second semiconductor portion forming a channel region of the first transistor. The first conductive layer includes a first conductive portion connected to a stable voltage source, an orthographic projection of the first conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate, and the first conducting portion and the first conductor portion form two electrodes of a parallel-plate capacitor.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

A thin film transistor according to an exemplary embodiment includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and an input region and an output region disposed on both sides of the channel region and doped with an impurity; a buffer layer disposed between the substrate and the semiconductor layer; a control electrode overlapping the semiconductor layer; a gate insulation layer disposed between the semiconductor layer and the control electrode; and an input electrode connected to the input region and an output electrode connected to the output region, wherein the semiconductor layer includes polysilicon and is crystallized by a blue laser scan.

A manufacturing apparatus and a manufacturing method are provided. A manufacturing apparatus includes a chamber, and a stage disposed in the chamber. The stage includes an upper surface on which a target substrate is disposed, a lower surface opposite to the upper surface, a first side surface extending between the upper surface and the lower surface in a first direction, and a second side surface extending between the upper surface and the lower surface in a second direction perpendicular to the first direction. The first side surface is in a round shape, and at least a portion of the first side surface is convex toward an outside of the stage.