The present disclosure relates to the field of display technologies, and discloses a Thin Film Transistor, a method for preparing the same, an array substrate, a display panel and an apparatus. The TFT includes: a base substrate; an active layer; a source electrode; and a drain electrode; where the active layer, the source electrode, and the drain electrode are sequentially laminated on the base substrate; and a projection of the source electrode on the base substrate covers a projection of part of edges of the active layer on the base substrate.

The present invention discloses a mask, a manufacturing method thereof and a manufacturing method of a thin film transistor. The mask includes: a first substrate and phase shift patterns formed above the first substrate, wherein an opening area is formed between the adjacent phase shift patterns and a halftone pattern is formed at positions corresponding to the phase shift patterns and the opening area. In the present invention, when an active layer pattern, a source and a drain are formed through one patterning process by using the mask, the design of narrow channel of the thin film transistor can be realized. As the width of the channel region of the thin film transistor becomes narrow, the volume of the thin film transistor can be effectively reduced, and the super-miniaturization of the thin film transistor can be achieved.

An etchant composition is provided comprising a persulfate from 0.5 to 20 wt %; a fluoride compound from 0.01 to 2 wt %; an inorganic acid from 1 to 10 wt %; a N (nitrogen atom)-containing heterocyclic compound from 0.5 to 5 wt %; a chloride compound from 0.1 to 5 wt %; a copper salt from 0.05 to 3 wt %; an organic acid or an organic acid salt from 0.1 to 10 wt %; an electron-donating compound from at 0.1 to 5 wt %; and a solvent of the residual amount. Also provided is a method of manufacturing a display device by using the same.

A thin film transistor includes a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are on the substrate. The active layer includes a channel region between the source electrode and the drain electrode and the channel region includes an edge region along a channel length direction and a main region outside the edge region. The thin film transistor further includes an auxiliary layer, a projection of the auxiliary layer on the substrate is at least partially overlapped with a projection of the edge region of the channel region on the substrate, and the auxiliary layer is configured to enhance a turn-on voltage of the edge region of the channel region.

The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.

An active element array substrate including a substrate, a first metal layer, a first insulation layer, a semiconductor layer, a first patterned conductive layer, a second metal layer, a second insulation layer, and a second patterned conductive layer is provided. The semiconductor layer is disposed on the first insulation layer. The first patterned conductive layer is disposed on the first insulation layer and covers a partial region of the semiconductor layer. The second metal layer is disposed on the first patterned conductive layer. The second insulation layer is disposed on the second metal layer and covers at least a partial region of the second metal layer, the first patterned conductive layer, the semiconductor layer, and the first insulation layer. The second patterned conductive layer is disposed on the second insulation layer and overlapped with the first patterned conductive layer. A display panel is also provided.

A method of manufacturing a light emitting panel, a light emitting panel, and a display device are disclosed. The method includes providing a substrate, forming a first metal layer on the substrate, performing an oxidation process to the first metal layer to form an oxide layer on the first metal layer, forming a photoresist layer on the oxide layer, patterning the photoresist layer, the oxide layer, and the substrate, and stripping a patterned photoresist layer, and sequentially forming a first passivation layer, a color resist layer, a second passivation layer, and an indium tin oxide film layer on the oxide layer.

An array substrate manufacturing method, an array substrate formed by the method, and a liquid crystal apparatus are disclosed. The method includes steps of depositing a first metal layer to form a plurality of scanning lines; depositing a first insulating layer and performing a patterning process on the first insulating layer; depositing a semiconductor layer and a second metal layer to form a plurality of data lines and thin-film transistors; depositing a second insulating layer to form a plurality of contact holes; and depositing a transparent layer to form a plurality of pixel electrodes.

The present invention provides an array substrate, a method for manufacturing the same and a display device, and relates to technical field of displays. The method for manufacturing an array substrate comprises forming a metal layer on a substrate and removing superficial metallic oxide on the metal layer by a washing process. The method for manufacturing an array substrate according to the present inversion can remove the superficial metal oxide on the metal layer and improve the performance of a TFT.

Disclosed are a manufacturing method of an array substrate, an array substrate and a display device. The manufacturing method of the array substrate includes: providing a substrate; depositing and patterning a gate layer on the substrate; depositing a protective layer on the substrate covered with the gate layer by atomic layer deposition; and depositing and patterning an amorphous silicon layer and an ohmic contact layer on the protective layer. The uniform protective layer of the present disclosure reduces the influence on the field effect mobility of the thin film transistor, makes the display of the product more stable, and improves the display effect.