A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.

A method for forming a semiconductor device includes providing a substrate structure having a plurality of semiconductor fins disposed on a substrate and a hard mask layer on the semiconductor fins. A first insulating material layer is formed covering the semiconductor fins, the hard masks, and the spaces between the semiconductor fins. Next, a first etch back process is performed to remove a top portion of the first insulating material layer to expose a portion of each of the semiconductor fins. Then dopants are implanted into remaining portions of the first insulating material layer and diffused into the semiconductor fins to form impurity regions. Next, a second etch back process is performed to remove a top portion of the remaining first insulating material layer to remove the implanted dopants in the first insulating material layer. Thereafter, a second insulating material layer is formed overlying the remaining first insulating material layer.

An embodiment method of forming a source/drain region for a transistor includes forming a recess in a substrate, epitaxially growing a semiconductor material in the recess, amorphizing the semiconductor material, and doping the semiconductor material to form a source/drain region. In an embodiment, the doping utilizes either phosphorus or boron as the dopant. Also, the amorphizing and the doping may be performed simultaneously. The amorphizing may be performed at least in part by doping with helium.

A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing fins of first and second film stacks, sacrificial gates across and on the fins of the first and second film stacks, where the first and second film stacks include alternating first and second films, and where the first films extend through sidewall spacers on the sacrificial gates, selectively forming a first mask layer on the sidewall spacers and on the first films of the first film stack, depositing a first dopant layer on the substrate, heat-treating the substrate to diffuse dopants from the first dopant layer into the first films of the second film stack to form doped first films in the second film stack, and removing the first mask layer from the substrate. The processing steps may be repeated for the second film stack.

A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.

The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.

Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.