Fabricating a semiconductor device comprises: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; disposing an implant at least along a contact trench wall; and disposing an epitaxial enhancement portion below the contact trench and in contact with the implant.

A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

A power semiconductor device includes a source region in an active area, a gate structure in a peripheral area, and a plurality of trench diodes connected in series between the source region and the gate structure. Each of the plurality of trench diodes includes a first trench provided in a substrate material, an insulating layer provided over surfaces of the first trench, a first semiconductor material of a first conductivity type provided within the first trench, and a second semiconductor material of a second conductivity type provided within the first trench and disposed over the first semiconductor material in the first trench.

An integrated electronic device forming a power device and including: a semiconductor body; a first conductive region and a second conductive region, which extend over the semiconductor body, the second conductive region surrounding the first conductive region at a distance; and an edge termination structure, which is arranged between the first and second conductive regions and includes a dielectric region, which delimits an active area of the power device, and a semiconductive structure, which extends over the dielectric region and includes a plurality of diode chains, each diode chain including a plurality of first semiconductive regions of a first conductivity type and a plurality of second semiconductive regions of a second conductivity type, the first and second semiconductive regions being arranged in alternating fashion so as to form a series circuit including a plurality of first and second diodes, which are spaced apart from one another and have opposite orientations.

In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.

The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

A method for forming a trench diode for a power semiconductor device includes forming a first trench having a first opening and a second trench having a second opening in a substrate material, the second opening of the second trench being wider than the first opening of the first trench. An insulating layer is formed over surfaces of the first and second trenches. A first semiconductor material is provided within the first and second trenches, the first semiconductor material filling the first trench at least until the first opening is entirely plugged and partially filling the second trench so that a portion of the second opening remains open, the first semiconductor material having a first conductivity type. A second semiconductor material is provided within the second trench and over the first semiconductor material, the second semiconductor material having a second conductivity type that is different from the first conductivity type.

A semiconductor body having a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body is provided. At least two trenches extend from the first surface of the semiconductor body through the source region layer and the body region layer. In each of the trenches a gate electrode and a gate dielectric are formed. Diode regions are directly adjacent to each of the at least two trenches. The diode regions extend from the first surface of the semiconductor body through the source region layer and the body region layer. The diode regions include a first region and a second region. A doping concentration in the diode regions varies such that a doping concentration is higher near the first surface than at the bottom of the trench.

A semiconductor device includes a semiconductor substrate; a semiconductor element disposed on a first surface of the semiconductor substrate; an insulation film, which is disposed on the first surface of the semiconductor substrate to cover the semiconductor element and has first contact holes exposing a region in the first surface of the semiconductor substrate, and second contact holes exposing the semiconductor element; a first electrode electrically connected to a region in the first surface of the semiconductor substrate through the first contact holes; and a second electrode electrically connected to the semiconductor element through the second contact hole. The insulation film has a first surface, which is flattened and opposite from the first surface of the semiconductor substrate. An interval between the first surface of the insulation film and the first surface of the semiconductor substrate is equal along a planer direction of the semiconductor substrate.