A semiconductor module, including a semiconductor chip that includes a switching device having a control electrode, and a control terminal connected to the control electrode, a first resistance being formed between the control electrode and the control terminal and having a positive temperature coefficient, and a second resistance connected to the control terminal, the second resistance having a negative temperature coefficient. A temperature coefficient of a combined resistance at the control terminal is zero or negative.

A semiconductor module, including a semiconductor chip that includes a switching device having a control electrode, and a control terminal connected to the control electrode, a first resistance being formed between the control electrode and the control terminal and having a positive temperature coefficient, and a second resistance connected to the control terminal, the second resistance having a negative temperature coefficient. A temperature coefficient of a combined resistance at the control terminal is zero or negative.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

A bootstrap diode circuit includes an anode for coupling to a power supply voltage terminal and a cathode for coupling to a bootstrap voltage terminal. The bootstrap diode circuit also includes a high-voltage p-type metal-oxide-semiconductor (PMOS) transistor, having a source forming the cathode of the bootstrap diode circuit and a drain forming the anode of the bootstrap diode circuit. The high-voltage PMOS transistor has a breakdown voltage higher in magnitude than a voltage drop between a maximum bootstrap voltage and the power supply voltage.

A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.

Provided are a semiconductor device capable of preventing erroneous operation and providing a field plate effect, and a method of manufacturing the semiconductor device. In a diode, a gate electrode, a p.sup.+ source region, and an n-type body region are electrically coupled to one another. A contact region is disposed between the n-type body region and the p.sup.+ source region in a first surface of a semiconductor substrate.

An apparatus comprises a Laterally Diffused Metal Oxide Semiconductor (LDMOS) comprising a drain connectable to a drift region and a source connectable to a body region. A diode comprises a cathode electrically coupled to the drift region, wherein during an operating condition, the anode is charged to a bias voltage less than a high voltage applied to the drain and greater than a low voltage applied to the source. The anode is laterally displaced from the drain by a first distance. A first deep trench isolation (DTI) is proximate to the source and disposed to laterally surround the LDMOS. A shield junction is proximate to the first DTI and on an opposite side of the source, and electrically connected to the anode.

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.