A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

A display panel and a liquid crystal display device are provided by the present application. The display panel includes a thin film transistor, a data line, and a scanning line. The thin film transistor includes an active layer, and the active layer includes a first section extending along a length direction of the data line and overlapping the data line, wherein the first section is electrically connected to the data line; a second section extending along the length direction of the data line; and a third section connecting the first section and the second section and extending along a length direction of the scanning line and overlapping the scanning line.

A TFT is provided that has a semiconductor layer in which one source drain region, one LDD region, a channel region, another LDD region, and a first portion of another source drain region extend along a first direction at a position overlapping a scanning line, and a second portion of the other source drain region extends along a second direction at a position overlapping a data line, a light shielding wall is disposed along the one LDD region or the other LDD region extending along the first direction, a substrate has a recessed portion in a region overlapping the light shielding wall, and a part of the light shielding wall is disposed along a side surface and a bottom surface of the recessed portion.

Provided is a thin film transistor, including: a base that includes, on an upper surface, a first region and a second region; a gate electrode that is provided on the first region of the base; a gate insulating film that is provided on a surface of the gate electrode and the second region of the base; and a semiconductor layer that is provided on a surface of the gate insulating film, wherein the semiconductor layer includes a third region and a fourth region, in the third region, the semiconductor layer and the gate electrode face with a minimum interval, in the fourth region, a distance from the semiconductor layer to the gate electrode is larger than the minimum interval, and at a boundary position between the third region and the fourth region, the semiconductor layer forms a linear shape or a substantially linear shape.

A liquid crystal apparatus includes a scan line extending in a ±X direction, a data line extending in a ±Y direction that intersects with the ±X direction, a TFT having a semiconductor layer in which, at a position overlapping with the scan line in plan view, one source drain region and a channel region extend along the ±X direction, and at a position overlapping with the data line in plan view, another source drain region extends along the ±Y direction, and a first upper capacitance element and a second upper capacitance element provided at a position overlapping with the data line, so as to overlap with the other source drain region in plan view.

A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi.sub.2 contact layer located between the source and the source electrode and between the drain and the drain electrode.

A method for making a thin film transistor device includes forming a semiconductor film on a flexible substrate comprising a thin ribbon of refractory material that does not degrade when heated to temperatures greater than about 750° C. The semiconductor film is crystallized by heating the semiconductor film and the flexible substrate to at least about 750° C. A dielectric material is deposited on the crystallized semiconductor film. Gate, source, and drain electrodes are formed on the dielectric material.

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.