Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

The present application relates to an active switch, a manufacturing method thereof and a display device. The manufacturing method of the active switch includes: sequentially forming a gate electrode, a gate insulating layer, an active layer, a semiconductor composite layer and a source electrode and a drain electrode on a substrate. The semiconductor composite layer includes a first N-type heavily doped amorphous silicon layer, a first N-type lightly doped amorphous silicon layer, a second N-type heavily doped amorphous silicon layer and a second N-type lightly doped amorphous silicon layer which are sequentially stacked, where the ion doping concentration of the first N-type heavily doped amorphous silicon layer is lower than that of the second N-type heavily doped amorphous silicon layer, and the ion doping concentration of the first N-type lightly doped amorphous silicon layer is higher than that of the second N-type lightly doped amorphous silicon layer.

A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer over the semiconductor layer, and a conductive layer over the first insulating layer. The semiconductor layer includes a first region, a pair of second regions, a pair of third regions, and a pair of fourth regions. The second regions sandwich the first region, the third regions sandwich the first region and the second regions, and the fourth regions sandwich the first region, the second regions, and the third regions. The first region includes a region overlapping with the first insulating layer and the conductive layer, the second regions and the third regions each include a region overlapping with the first insulating layer and not overlapping with the conductive layer, and the fourth regions overlap with neither the first insulating layer nor the conductive layer. A thickness of the first insulating layer in regions overlapping with the second regions is substantially equal to a thickness of the first insulating layer in a region overlapping with the first region. A thickness of the first insulating layer in regions overlapping with the third regions is smaller than the thickness of the first insulating layer in the regions overlapping with the second regions.

This disclosure provides a display device, an array substrate, a thin film transistor and a fabrication method thereof. The thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a dielectric layer, a source electrode and a drain electrode. The active layer has a channel region, doped regions at both sides of the channel region, and buffer regions each of which arranged between the corresponding doped region and the channel region, and a doping concentration of the buffer regions is less than that of the doped regions. The gate insulating layer is at a side of the active layer, covers the channel region and the buffer regions, and exposes the doped regions. The gate electrode is on a surface of the gate insulating layer facing away from the active layer.

The present application discloses an oxide thin film transistor, a display panel, and a preparation method thereof. Each thickness of the first gate insulating layer of the present application corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region; and thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region. The the first gate insulating layer effectively shields the first channel region laterally.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern.

Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.

A thin film transistor (TFT) substrate is disclosed. The TFT substrate includes a substrate, a blocking layer, a source electrode, and a drain electrode on a same layer over the substrate, an active layer overlapping the blocking layer, the source electrode, and the drain electrode, a gate insulation layer over the active layer, a first gate electrode over the gate insulation layer, an interlayer dielectric over the first gate electrode, a first connection electrode over the interlayer dielectric and connected to the active layer and the source electrode through a first contact hole, a second connection electrode over the interlayer dielectric and connected to the active layer and the drain electrode through a second contact hole, a planarization layer over the first connection electrode and the second connection electrode, and a pixel electrode over the planarization layer and connected to the second connection electrode through a third contact hole.

An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.