A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.

An aspect of the present invention provides a metal pillar in a columnar shape formed by cutting a metal wire to a predetermined length. The metal pillar has a burr length of 0.1 to 0.5 ?m on the cutting surface, an electrical conductivity of 11 to 101% IACS, and a Vickers hardness of 150 to 300 HV.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a bottom side, a bottom coating located on the bottom side and an electrode layer located on an underside of the bottom coating facing away from the semiconductor layer sequence, wherein the bottom coating has a thickness gradient and at least one ridge line at which the bottom coating is thickest, wherein the electrode layer extends over the at least one ridge line such that a contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape, and wherein an electrical and mechanical contact plane of the contact side parallel to the bottom side is defined by the at least one ridge line.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a bottom side, a bottom coating located on the bottom side and an electrode layer located on an underside of the bottom coating facing away from the semiconductor layer sequence, wherein the bottom coating has a thickness gradient and at least one ridge line at which the bottom coating is thickest, wherein the electrode layer extends over the at least one ridge line such that a contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape, and wherein an electrical and mechanical contact plane of the contact side parallel to the bottom side is defined by the at least one ridge line.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

In an MEMS device, in a Z direction that is a direction in which a first core portion, a plurality of first bump wiring, and a plurality of first individual wiring are laminated, a width between the first core portion and a wiring substrate is wider than a maximum particle diameter of solid particles contained in an adhesive, and a width between a first wiring and a second wiring and a width between a third wiring and a fourth wiring are wider than the maximum particle diameter of the solid particles.

In an MEMS device, in a Z direction that is a direction in which a first core portion, a plurality of first bump wiring, and a plurality of first individual wiring are laminated, a width between the first core portion and a wiring substrate is wider than a maximum particle diameter of solid particles contained in an adhesive, and a width between a first wiring and a second wiring and a width between a third wiring and a fourth wiring are wider than the maximum particle diameter of the solid particles.

Provided is an electronic device including a display panel including pixels, and first pads respectively including pad parts which are disposed in one direction and respectively electrically connected to the pixels, and conductive members electrically connected to the pad parts, a circuit board including second pads disposed in the one direction and respectively electrically connected to the first pads, and an adhesive layer disposed between the display panel and the circuit board. The conductive members each include a first member disposed on the pad part and having an insulation property, a second member covering the first member and connected to the pad part, and a third member disposed on the second member while exposing a portion of the second member and including a material different from a material of the second member.

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.