Embodiments may relate to a microelectronic package that includes a die and a backside metallization (BSM) layer positioned on the face of the die. The BSM layer may include a feature that indicates that the BSM layer was formed on the face of the die by a masked deposition technique. Other embodiments may be described or claimed.

A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.

A semiconductor device manufacturing method, includes: a preparing process for preparing a conductive plate, a semiconductor chip arranged over the conductive plate with a first bonding material therebetween, and a connection terminal including a bonding portion arranged over the semiconductor chip with a second bonding material therebetween; a first jig arrangement process for arranging a first guide jig, through which a first guide hole pierces, over the conductive plate, such that the first guide hole corresponds to the bonding portion in a plan view of the semiconductor device; and a first pressing process for inserting a pillar-shaped pressing jig, which includes a pressing portion at a lower end portion thereof, into the first guide hole, and pressing the bonding portion of the connection terminal to a side of the conductive plate with the pressing portion.

There is provided a manufacturing method for an insulating resin circuit substrate, which is a manufacturing method for an insulating resin circuit substrate which includes an insulating resin layer composed of a polyimide resin and a circuit layer consisting of metal pieces disposed in a circuit pattern shape on one surface of the insulating resin layer. The manufacturing method includes a temporary fixing step of pressurizing the metal pieces toward the resin sheet material while heating the metal pieces to temporarily fix the metal pieces and a joining step of disposing a cushion material on a side of the metal pieces which are temporarily fixed and pressurizing the metal pieces and the resin sheet material in a laminating direction, while heating the metal pieces and the resin sheet material, to join the resin sheet material and the metal pieces.

Processes of joining substrates via transient liquid phase bonding (TLPB). The processes include providing an interlayer of a low melting temperature phase (LTP) that includes Sn and Bi between and in contact with at least two substrates, and heating the substrates and the interlayer therebetween at a processing temperature equal to or above 200° C. such that the interlayer liquefies and the LTP interacts with high melting temperature phases (HTPs) of the substrates to yield isothermal solidification of the interlayer. The processing temperature is maintained for a duration sufficient for the interlayer to be completely consumed and a solid bond is formed between the substrates. Also provided are assemblies formed by the above noted processes.

Processes of joining substrates via transient liquid phase bonding (TLPB). The processes include providing an interlayer of a low melting temperature phase (LTP) that includes Sn and Bi between and in contact with at least two substrates, and heating the substrates and the interlayer therebetween at a processing temperature equal to or above 200° C. such that the interlayer liquefies and the LTP interacts with high melting temperature phases (HTPs) of the substrates to yield isothermal solidification of the interlayer. The processing temperature is maintained for a duration sufficient for the interlayer to be completely consumed and a solid bond is formed between the substrates. Also provided are assemblies formed by the above noted processes.

A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.