Disclosed is a semiconductor package comprising a package substrate having a mount region and a peripheral region that surrounds the mount region, a semiconductor device on the mount region of the package substrate, a package cap on the peripheral region of the package substrate and including a partition portion that surrounds the semiconductor device and an extension portion that covers the semiconductor device, and an adhesive layer between the package substrate and a bottom surface of the package cap. The bottom surface of the package cap has a trench. The trench has a trapezoidal cross-section whose width decreases in a direction receding from the bottom surface of the package cap. The adhesive layer is in contact with a top surface of the package substrate and the bottom surface of the package cap. The adhesive layer fills the trench.

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.

The invention provides a power module substrate with a heat sink, which includes a power module substrate provided with an insulating substrate, a circuit layer provided on one surface of the insulating substrate and a metal layer provided on the other surface of the insulating substrate. The heat sink is bonded to the power module substrate via a bonding layer (30) to a surface on an opposite side to the insulating substrate of the metal layer. Bonding layer is a sintered body of silver particles, a porous body having a relative density in a range of 60% or more and 90% or less, and having a thickness in a range of 10 μm or more and 500 μm or less.

The invention provides a power module substrate with a heat sink, which includes a power module substrate provided with an insulating substrate, a circuit layer provided on one surface of the insulating substrate and a metal layer provided on the other surface of the insulating substrate. The heat sink is bonded to the power module substrate via a bonding layer (30) to a surface on an opposite side to the insulating substrate of the metal layer. Bonding layer is a sintered body of silver particles, a porous body having a relative density in a range of 60% or more and 90% or less, and having a thickness in a range of 10 μm or more and 500 μm or less.

The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.

The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.

A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate bonded to an upper surface of the semiconductor element with an adhesive, and an encapsulation resin that fills a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body overlapped with the semiconductor element in a plan view. The body is larger than the semiconductor element in a plan view. A projection is formed integrally with the body. The projection projects outward from an end of the body and is located at a lower position than the body. The encapsulation resin covers upper, lower, and side surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.

A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate bonded to an upper surface of the semiconductor element with an adhesive, and an encapsulation resin that fills a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body overlapped with the semiconductor element in a plan view. The body is larger than the semiconductor element in a plan view. A projection is formed integrally with the body. The projection projects outward from an end of the body and is located at a lower position than the body. The encapsulation resin covers upper, lower, and side surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.