A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes placing a first semiconductor chip on a carrier with the first main surface of the first semiconductor chip facing the carrier. A first layer of soft solder material is provided between the first main surface and the carrier. Heat is applied during placing so that a temperature at the first layer of soft solder material is equal to or higher than a melting temperature of the first layer of soft solder material. A second layer of soft solder material is provided between the first contact area and the second main surface. Heat is applied during placing so that a temperature at the second layer of soft solder material is equal to or higher than a melting temperature of the second layer of soft solder material. The first and second layers of soft solder material are cooled to solidify the soft solder materials.

A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A method includes providing a substrate having substrate terminals and providing a first component having a first terminal and a second terminal. The method includes providing a clip structure having a first clip, a second clip, and a clip connector coupling the first clip to the second clip. The method includes coupling the first clip to the first terminal and a substrate terminal and coupling the second clip to another substrate terminal. The method includes encapsulating the structure and removing a portion of the clip connector. In some examples, the first portion of the clip connector includes a first portion surface, the second portion of the clip connector includes a second portion surface, and the first portion surface and the second portion surface are exposed from a top side of the encapsulant. Other examples and related structures are also disclosed herein.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.

The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

In this power semiconductor module, a first lead frame and a second lead frame through which currents flow in opposite directions are arranged so as to overlap each other, whereby the internal inductance can be reduced. In a direction perpendicular to one main surface of a first metal wiring layer, each of the first lead frame and the second lead frame is provided so as not to overlap parts of end surfaces of the first metal wiring layer and a second metal wiring layer. Thus, in a manufacturing process for the power semiconductor module before sealing with sealing resin, it is possible to easily perform positioning between the lead frames and between the metal wiring layer and the lead frame, using the end surfaces, whereby the manufacturing process can be simplified.