The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion.

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion.

Provided is a semiconductor package using a conductive metal structure, and more particularly, to a semiconductor package using a conductive metal structure formed in a clip or a column, through which a semiconductor chip and a lead of a lead frame are electrically connected to each other and an area where the semiconductor chip and the metal structure are adhered may be effectively improved so that productivity may increase and durability and electrical connection properties may be improved. The semiconductor package according to the present invention includes: a semiconductor chip; an aluminum pad formed on an upper part of the semiconductor chip; and a conductive metal structure adhered to the aluminum pad by a solder-based second adhesive layer, wherein the second adhesive layer includes intermetallic compounds (IMC) distributed to a lower fixed part thereof near the aluminum pad.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.