Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

A semiconductor device includes a wiring substrate including an opening formed to penetrate from a first main surface to a second main surface, and configured to include an insulating material, a metal substrate fixed to the wiring substrate to cover the opening from the second main surface side, a semiconductor chip fixed inside the opening on a main surface of the metal substrate, a resin disposed to cover the semiconductor chip from above the first main surface on the main surface, and formed of a material having a thermal expansion coefficient different from that of the wiring substrate, and an adhesive containing a metal paste disposed between a side surface of the wiring substrate and the main surface, and the resin, in which the adhesive is disposed on the main surface so that a thickness gradually increases from a center side of the opening to the side surface.

A semiconductor package is disclosed. The semiconductor package includes a package substrate. The semiconductor package includes a semiconductor die having a first surface attached to the package substrate and a second surface. The semiconductor package includes a heat sink attached to the second surface of the semiconductor die. The semiconductor package includes a heat dissipation layer interposed between the heat sink and the semiconductor die. The heat dissipation layer comprises one or more high-k dielectric materials.

Embodiments of the present invention relate to the field of soldering sheets, and provided therein are an ultra-thin soldering gasket and a preparation method therefor, a soldering method, and a semiconductor device. The ultra-thin soldering gasket comprises: an internal support structure and a solder layer which covers a surface of the internal support structure, the solder layer being formed by uniformly attaching a solder liquid to the surface of the internal support structure. The preparation method for an ultra-thin soldering gasket comprises the following steps: immersing an internal support structure that has passed through a surface treatment process into a solder liquid, then removing same, and cooling. The soldering method based on the ultra-thin soldering gasket comprises: placing an ultra-thin soldering gasket between soldering surfaces to be soldered, and then performing reflux soldering to form a semiconductor device. The ultra-thin soldering gasket is flat and is not warped, solders are uniform, the minimum thickness of a single layer is only five micrometers, and high-accuracy soldering requirements can be met.

There are provided an adhesive film for a semiconductor including: a conductive layer containing at least one metal selected from the group consisting of copper, nickel, cobalt, iron, stainless steel (SUS), and aluminum, and having a thickness of 0.05 m or more; and an adhesive layer formed on at least one surface of the conductive layer and including a (meth)acrylate-based resin, a curing agent, and an epoxy resin, and a semiconductor device including the above-mentioned adhesive film.

There are provided an adhesive film for a semiconductor including: a conductive layer containing at least one metal selected from the group consisting of copper, nickel, cobalt, iron, stainless steel (SUS), and aluminum, and having a thickness of 0.05 m or more; and an adhesive layer formed on at least one surface of the conductive layer and including a (meth)acrylate-based resin, a curing agent, and an epoxy resin, and a semiconductor device including the above-mentioned adhesive film.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.

A power electronics assembly includes a substrate, a semiconductor device and a metal inverse opal (MIO) bonding layer positioned between and bonded to the substrate and the semiconductor device. A first electrode is disposed on a first surface, a second electrode is disposed on a second surface, and a third electrode is disposed on a third surface. The first surface may be a top surface of the semiconductor device, the second surface may be a bottom surface of the semiconductor device, the third surface may be spaced apart from the bottom surface of the semiconductor device, and the second electrode is in electrical communication with the third electrode through the MIO bonding layer. A cooling fluid circuit with a cooling fluid inlet, a cooling fluid outlet and a cooling fluid path through the MIO bonding layer may be included.