Patent classifications
H01L2224/29164
Wafer level flat no-lead semiconductor packages and methods of manufacture
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
Wafer level flat no-lead semiconductor packages and methods of manufacture
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
SEMICONDUCTOR ELEMENT BONDING BODY, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT BONDING BODY
A semiconductor element bonding body including: a substrate, in which a concave portion is formed; and a semiconductor element placed in the concave portion to be mounted to the substrate. A portion of the substrate in which the concave portion is formed is made of Cu. The concave portion has a perimeter portion in which a level difference is formed, and the level difference has a height d of 20 m or more and less than 50 m. The concave portion has a bottom surface having a flatness degree of /8.7 m or more and /1.2 m or less when a wavelength of a laser is 632.8 nm. A metal film is formed on the semiconductor element, and the bottom surface of the concave portion and the metal film are bonded directly to each other.
Copper paste for joining, method for manufacturing joined body, and method for manufacturing semiconductor device
Provided is a copper paste for joining including copper particles, second particles including a metal element other than copper, and a dispersion medium, in which the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 m or more and 0.8 m or less and micro copper particles having a volume-average particle diameter of 2 m or more and 50 m or less, a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles, the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, and a content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles.
METHOD OF FASTENING A SEMICONDUCTOR CHIP ON A LEAD FRAME, AND ELECTRONIC COMPONENT
A method of attaching a semiconductor chip to a lead frame, including A) providing a semiconductor chip, B) applying a solder metal layer sequence on the semiconductor chip, C) providing a lead frame, D) applying a metallization layer sequence on the lead frame, E) applying the semiconductor chip on the lead frame via the solder metal layer sequence and the metallization layer sequence, and F) heating the arrangement produced under E) to attach the semiconductor chip to the lead frame, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer including gold arranged between the barrier layer and the semiconductor chip.
METHOD OF FASTENING A SEMICONDUCTOR CHIP ON A LEAD FRAME, AND ELECTRONIC COMPONENT
A method of attaching a semiconductor chip to a lead frame, including A) providing a semiconductor chip, B) applying a solder metal layer sequence on the semiconductor chip, C) providing a lead frame, D) applying a metallization layer sequence on the lead frame, E) applying the semiconductor chip on the lead frame via the solder metal layer sequence and the metallization layer sequence, and F) heating the arrangement produced under E) to attach the semiconductor chip to the lead frame, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer including gold arranged between the barrier layer and the semiconductor chip.
Wafer level flat no-lead semiconductor packages and methods of manufacture
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
Wafer level flat no-lead semiconductor packages and methods of manufacture
Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
Solid-state wafer bonding of functional materials on substrates and self-aligned contacts
A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.
COPPER PASTE FOR JOINING, METHOD FOR MANUFACTURING JOINED BODY, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a copper paste for joining including copper particles, second particles including a metal element other than copper, and a dispersion medium, in which the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 m or more and 0.8 m or less and micro copper particles having a volume-average particle diameter of 2 m or more and 50 m or less, a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles, the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, and a content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles.