Patent classifications
H01L2224/29171
OPTICAL SEMICONDUCTOR APPARATUS
An optical semiconductor apparatus includes: an optical semiconductor device including a translucent support substrate; a buffer layer on the support substrate, a seal ring in a frame shape provided in an outer region on the buffer layer, an active layer provided on an inner region of the buffer layer, and an electrode provided on the active layer. The optical semiconductor apparatus further including: a package substrate on which the optical semiconductor device is mounted; and a sealing part that seals a space between the seal ring and the package substrate.
BACK SIDE METALLIZATION THIN FILM STRUCTURE AND METHOD FOR FORMING THE SAME
A back side metallization thin film structure is provided, which includes a wafer and a metallic nano-twinned thin film on the back side of the wafer. A plurality of integrated circuit devices are formed on the front side of the wafer. The metallic nano-twinned thin film includes silver, copper, gold, palladium, or nickel. The metallic nano-twinned thin film has a transition layer near the wafer and a twin layer away from the wafer. The twin layer accounts for at least 70% of the thickness of the metallic nano-twinned thin film and includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include more than 50% of (111) crystal orientation. The back side metallization thin film structure is formed by activating the wafer surface by ion beam bombardment, followed by an evaporation deposition process performed on the activated wafer surface with simultaneous ion beam bombardment.
Micro-bonding structure
A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.
Micro-bonding structure
A micro-bonding structure including a substrate, a conductive pad, a bonding layer, a micro device, and a diffusive bonding portion is provided. The conductive pad is present on the substrate. The bonding layer is present on the conductive pad. The micro device is present on the bonding layer. The diffusive bonding portion is present between and electrically connected with the bonding layer and the conductive pad. The diffusive bonding portion consists of at least a part of elements from the bonding layer and at least a part of elements from the conductive pad. A plurality of voids are present between the bonding layer and the conductive pad, and one of the voids is bounded by the diffusive bonding portion and at least one of the conductive pad and the bonding layer.
SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF
The present disclosure discloses a semiconductor apparatus and method of manufacturing. The apparatus includes: a circuit device and a heat sink fin that are disposed in a laminated manner, and a thermal interface material layer located between the circuit device and the heat sink fin. A packaging layer is disposed around a side wall of the circuit device. A first surface of the thermal interface material layer is thermally coupled to the circuit device and the packaging layer, and a second surface is thermally coupled to the heat sink fin. In the foregoing solution, the packaging layer and the circuit device are both thermally coupled to the thermal interface material layer, a contact area between the circuit device and the thermal interface material layer is increased.
Low temperature high reliability alloy for solder hierarchy
A lead-free, antimony-free solder alloy_suitable for use in electronic soldering applications. The solder alloy comprises (a) from 1 to 4 wt. % silver; (b) from 0.5 to 6 wt. % bismuth; (c) from 3.55 to 15 wt. % indium, (d) 3 wt. % or less of copper; (e) one or more optional elements and the balance tin, together with any unavoidable impurities.
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region.
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region.
PHASE CHANGING THERMAL INTERFACE MATERIAL ALLOY CREATED IN-SITU
Thermal interface materials deposited in solid form, in a layered manner, and their uses in electronics assembly are described. In one implementation, a method includes: forming an assembly including multiple solid metal thermal interface materials (TIMs) between a first device and a second device such that a first surface of the solid metal TIMs is in touching relation with a surface of the first device, and a second surface of the solid metal TIMs opposite the first surface is in touching relation with a surface of the second device, the solid metal TIMs including a first solid metal TIM and a second solid metal TIM; and forming a liquid TIM alloy from the solid metal TIMs by heating the assembly above a first solidus temperature of the first solid metal TIM, the liquid TIM alloy having a second solidus temperature below the first solidus temperature.
Semiconductor light emitting device including cap structure and method of making same
A light emitting device and method of forming the same, the light emitting device including: a substrate, a buffer layer disposed on the substrate, a semiconductor mesa disposed on the buffer layer and including a first semiconductor layer, a light emitting active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer, a contact layer disposed on an upper surface of the mesa, a passivation layer covering sidewalls of the mesa and the contact layer, and a cap structure including a reflective layer covering an upper surface of the contact layer, and a solder layer including a recess in which the reflective layer is disposed.