A method of producing a semiconductor device includes steps of: growing semiconductor layers to form a semiconductor stack on a semiconductor substrate; forming a first adhesive layer on the semiconductor stack; bonding a temporary support made of non-semiconductor material to the first adhesive layer; removing the semiconductor substrate from the semiconductor stack to expose a surface of the semiconductor stack; forming a second adhesive layer on the exposed surface of the semiconductor stack; bonding a support to the second adhesive layer; and removing the temporary support from the semiconductor stack. The support has a thermal conductivity greater than the thermal conductivities of the semiconductor layer in the semiconductor stack. In forming the first adhesive layer, this layer can cover the entire surface, or both the top and a side of the semiconductor stack. Before forming the first adhesive layer, a protective layer can be formed on the semiconductor stack.

A method of producing a semiconductor device includes steps of: growing semiconductor layers to form a semiconductor stack on a semiconductor substrate; forming a first adhesive layer on the semiconductor stack; bonding a temporary support made of non-semiconductor material to the first adhesive layer; removing the semiconductor substrate from the semiconductor stack to expose a surface of the semiconductor stack; forming a second adhesive layer on the exposed surface of the semiconductor stack; bonding a support to the second adhesive layer; and removing the temporary support from the semiconductor stack. The support has a thermal conductivity greater than the thermal conductivities of the semiconductor layer in the semiconductor stack. In forming the first adhesive layer, this layer can cover the entire surface, or both the top and a side of the semiconductor stack. Before forming the first adhesive layer, a protective layer can be formed on the semiconductor stack.

A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m.sup.2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in m) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package includes a component on a substrate. The component can include one or more semiconductor dies. The package can also include a multi-reference integrated heat spreader (IHS) solution (also referred to as a smart IHS solution), where the smart IHS solution includes a smart IHS lid. The smart IHS lid includes a cavity formed in a central region of the smart lid. The smart IHS lid can be on the component, such that the cavity corresponds to the component. A first thermal interface material layer (TIM-layer 1) can be on the component. An individual IHS lid (IHS slug) can be on the TIM-layer 1. The IHS slug can be inserted into the cavity. Furthermore, an intermediate thermal interface material layer (TIM-1A layer) can be between the IHS slug and the cavity.

Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package includes a component on a substrate. The component can include one or more semiconductor dies. The package can also include a multi-reference integrated heat spreader (IHS) solution (also referred to as a smart IHS solution), where the smart IHS solution includes a smart IHS lid. The smart IHS lid includes a cavity formed in a central region of the smart lid. The smart IHS lid can be on the component, such that the cavity corresponds to the component. A first thermal interface material layer (TIM-layer 1) can be on the component. An individual IHS lid (IHS slug) can be on the TIM-layer 1. The IHS slug can be inserted into the cavity. Furthermore, an intermediate thermal interface material layer (TIM-1A layer) can be between the IHS slug and the cavity.