A multilayer composite bonding material with a plurality of thermal stress compensation layers is provided. The plurality of thermal stress compensation layers include a metal core layer, a pair of particle layers extending across the metal core layer such that the metal core layer is sandwiched between the pair of particle layers, and a pair of metal outer layers extending across the pair of particle layers such that the pair of particle layers are sandwiched between the pair of metal outer layers. A pair of low melting point (LMP) bonding layers extend across the pair of metal outer layers. The metal core layer, the pair of particle layers, and the pair of metal outer layers each have a melting point above a transient liquid phase (TLP) sintering temperature, and the pair of LMP bonding layers each have a melting point below the TLP sintering temperature.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.

A cooling bond layer for a power electronics assembly is provided. The cooling bond layer includes a first end, a second end spaced apart from the first end, a metal matrix extending between the first end and the second end, and a plurality of micro-channels extending through the metal matrix from the first end to the second end. The plurality of micro-channels are configured for a cooling fluid to flow through and remove heat from the cooling bond layer. In some embodiments, the plurality of micro-channels are cylindrical shaped micro-channels. In such embodiments, the plurality of micro-channels may have a generally constant average inner diameter along a thickness of the cooling bond layer. In the alternative, the plurality of micro-channels may have a graded average inner diameter along a thickness of the cooling bond layer. In other embodiments, the plurality of micro-channels may have a wire mesh layered structure.

A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.

A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.

A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.

A semiconductor device includes a wiring, a semiconductor chip above the wiring and a metal block above the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a lower electrode, an upper large electrode and an upper small electrode. The semiconductor chip includes a first portion and a second portion, the first portion being on an upper small electrode side with respect to a centroid of the semiconductor chip, the second portion being on an opposite side of the upper small electrode with respect to the centroid. The lower electrode is connected to the wiring via a lower solder layer. The lower solder layer includes a solder base material and metal particles. A volume ratio of the metal particles occupying the lower solder layer under the second portion is higher than a volume ratio of the metal particles occupying the lower solder layer under the first portion.

Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11. Since the linear expansion coefficient of the base plate 11 is set close to that of the semiconductor chip 13, a displacement occurring between the base plate 11 and the semiconductor chip 13 in response to a temperature change is relatively small.

Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11. Since the linear expansion coefficient of the base plate 11 is set close to that of the semiconductor chip 13, a displacement occurring between the base plate 11 and the semiconductor chip 13 in response to a temperature change is relatively small.

An integrated circuit chip attachment in a microstructure device is accomplished through the use of an adhesive-based material in which graphene flakes are incorporated. This results in superior thermal conductivity. The spatial orientation of the graphene flakes is controlled, for example by adhering polar molecules to the graphene flakes and exposing the flakes to an external force field, so that the graphene flakes have desired orientations under the integrated circuit chip, alongside of the integrated circuit chip and above the integrated circuit chip.