A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

A manufacturing method includes the step of forming a diced semiconductor wafer (10) including semiconductor chips (11) from a semiconductor wafer (W) typically on a dicing tape (T1). The diced semiconductor wafer (10) on the dicing tape (T1) is laminated with a sinter-bonding sheet (20). The semiconductor chips (11) each with a sinter-bonding material layer (21) derived from the sinter-bonding sheet (20) are picked up typically from the dicing tape (T1). The semiconductor chips (11) each with the sinter-bonding material layer are temporarily secured through the sinter-bonding material layer (21) to a substrate. Through a heating process, sintered layers are formed from the sinter-bonding material layers (21) lying between the temporarily secured semiconductor chips (11) and the substrate, to bond the semiconductor chips (11) to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to individual semiconductor chips while reducing loss of the sinter-bonding material.

There is provided a semiconductor device including: a semiconductor element; a support substrate configured to support the semiconductor element; an intermediate metal layer interposed between the semiconductor element and the support substrate in a thickness direction of the support substrate, wherein the semiconductor element and the intermediate metal layer are bonded by solid phase diffusion bonding; and a first positioning portion including a portion of the semiconductor element and a first portion of the intermediate metal layer and configured to suppress relative movement between the semiconductor element and the intermediate metal layer.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

An electronic device includes a substrate and a wiring. The wiring is provided above the substrate and includes a NiB layer and a copper layer provided on the NiB layer. The NiB layer contains 3.2% by weight to 5% by weight of boron.

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.