A chip package structure and a manufacturing method are provided. The chip package structure includes a substrate, a first chip, an insulating layer and a plurality of routing layers. The substrate has a first metal pad and a second metal pad. The first chip is disposed on the first metal pad. The insulating layer is disposed on the substrate and partially covers the first metal pad, the second metal pad and the first chip. The plurality of routing layers are disposed on the substrate and electrically connected to the first metal pad, the second metal pad and the first chip.

Aspects disclosed include an integrated circuit (IC) package with die interconnects of a semiconductor die terminating at multiple metallization layers in a substrate to reduce spacing requirement between die interconnects. The die comprises a first plurality of die interconnects and a second plurality of die interconnects. The substrate includes a first metallization layer adjacent to the die and a second metallization layer that is parallel to the first metallization layer such that the first metallization layer is between the die and second metallization layer. The first and second metallization layers each comprise a respective first plurality of metal pads and a second plurality of metal pads. The first plurality of die interconnects terminates to the first plurality of metal pads in the first metallization layer while the second plurality of die interconnects terminates to the second plurality of metal pads in the second metallization layer.

A heat dissipation structure is provided. The heat dissipation structure according to an aspect of the present disclosure includes a PCB substrate having a first heat dissipation pad having a predetermined area on one surface; a heating element coupled onto the heat dissipation pad by a coupling part, the heating element having one surface disposed adjacent to the heat dissipation pad and the other surface opposite to the one surface; a heat sink having one surface disposed of contact on the heating element; and a heat transfer material comprising a first region portion interposed between the other surface of the heating element and one surface of the heat sink.

The present disclosure describes a method to form a semiconductor structure having an oxide structure on a wafer edge. The method includes forming a device layer on a first substrate, forming an interconnect layer on the device layer, forming an oxide structure on a top surface and along a sidewall surface of the interconnect layer, forming a bonding layer on the oxide structure and the interconnect layer, and bonding the device layer to a second substrate with the bonding layer.