A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.

A semiconductor package includes; a lower connection structure, a semiconductor chip on the lower connection structure, an intermediate connection structure on the lower connection structure, a sealing layer covering the semiconductor chip, and an upper connection structure including a first upper insulating layer on the sealing layer, a first upper conductive pattern layer on the first upper insulating layer, and a first upper via penetrating the first upper insulating layer to directly connect the first upper conductive pattern layer to the intermediate connection structure. A height from an upper surface of the lower connection structure to an upper surface of the sealing layer is less than or equal to a maximum height from the upper surface of the lower connection structure to an upper surface of the intermediate connection structure.

An housing for electronic components, such as LEDs and/or FETs, is provided. The housing has a base body having an upper surface that at least partially defines a mounting area for an electronic functional element, such that the base body provides a heat sink for the electronic functional element. The base body has a lower surface and a lateral surface and includes a connecting body for the electronic functional element, which is joined to the base body a glass layer formed by an alkali titanium silicate glass.

The present disclosure is related to electronic modules for electronic components and methods for manufacturing the same. In one embodiment, an electronic module is formed using a first substrate having a first component area and a second substrate having a second component area. One or more electronic components may be attached to both the first component area and the second component area. The second substrate is mounted over the first substrate such that the second component area faces the first component area. An overmold covers the first component area and the second component area so as to cover the electronic components on both the first component area and the second component area. In this manner, the number of electronic components within the electronic module that can be mounted on an area of a printed circuit board (PCB) is increased.

Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

A semiconductor package includes a frame having a first surface, a second surface opposite the first surface, and a through-hole, a first semiconductor chip in the through-hole of the frame, a second semiconductor chip on the frame, a first connection structure on the first surface of the frame and including a first redistribution structure electrically connected to the first semiconductor chip and having a third surface contacting the first surface of the frame, the first redistribution structure including a first redistribution layer and a first redistribution via, a first pad on a center portion of a fourth surface of the first redistribution structure opposite the third surface, a second pad on an edge portion of the fourth surface, a second connection structure on the second surface and comprising a second redistribution structure electrically connected to the second semiconductor chip and including a second redistribution layer and a second redistribution via, and an electrical connection metal on the first pad on the fourth surface, wherein the electrical connection metal is not on the second pad.

A semiconductor package structure includes a conductive structure, a semiconductor element disposed on and electrically connected to the conductive structure, a supporting structure, an encapsulant, and a metal layer. The supporting structure is disposed on the conductive structure and surrounds the semiconductor element. The encapsulant covers the semiconductor element. The metal layer is disposed on or embedded in the encapsulant.