There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.

A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

The semiconductor device includes a chip which has a main surface, a first region of a first conductivity type which is formed in a surface layer portion of the main surface, a second region of a second conductivity type which is formed in a surface layer portion of the first region, a trench separation structure which penetrates through the second region, surrounds an interior of the second region, and demarcates an inner region at an inner side of the second region and an outer region at an outer side of the second region in the main surface, a trench gate structure which is formed in the inner region, an inner diode which includes the first region and the second region that are positioned in the inner region, and an outer diode which includes the first region and the second region that are positioned in the outer region.

A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.

A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

A method of determining whether a silicon-carbide semiconductor device, which has a metal oxide semiconductor (MOS) gate structure and a built-in diode, is a conforming product. The method includes measuring an ON voltage of the silicon carbide semiconductor device, passing a forward current through the built-in diode of the silicon carbide semiconductor device, measuring another ON voltage of the silicon carbide semiconductor device, which is the ON voltage of the silicon carbide semiconductor device after passing the forward current, calculating a rate of change between the ON voltage and the another ON voltage, and determining that the silicon carbide semiconductor device is a conforming product unless the calculated rate of change is less than 3%.

A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n.sup.-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other.

A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facing the second silicon carbide region.