In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

A method for producing a semiconductor device includes forming transistor cells in a semiconductor body, each cell including a drift region separated from a source region by a body region, a gate electrode dielectrically insulated from the body region, and a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in a vertical direction. Forming the drift and compensation regions includes performing a first implantation step, thereby implanting first and second type dopant atoms into the semiconductor body, wherein an implantation dose of at least one of the first type dopant atoms and the second type dopant atoms for each of at least two sections of the semiconductor body differs from the implantation dose of the corresponding type of dopant atoms of at least one other section of the at least two sections.

A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including electrodes on a front surface side and a back surface side thereof; and a graphite plate having an anisotropic thermal conductivity, the graphite plate of which one end is connected to the front surface side of the semiconductor device and the other end is connected to the insulating substrate, wherein heat of the front surface side of the semiconductor device is transferred to the insulating substrate through the graphite plate. There is provide an inexpensive power module capable of reducing a stress and capable of exhibiting cooling performance not inferior to that of the double-sided cooling structures.

A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied,

S1<S3, S1<S2, S3>S4.

A vertical metal oxide semiconductor field effect transistor, including a starting substrate of a first conductivity type, a second first-conductivity-type epitaxial layer provided on a first surface of the starting substrate via a first first-conductivity-type epitaxial layer, a first semiconductor region of the first conductivity type provided as a portion of the second first-conductivity-type epitaxial layer, a second-conductivity-type epitaxial layer forming a pn junction interface with the second first-conductivity-type epitaxial layer and supplying a minority carrier to the second first-conductivity-type epitaxial layer, a plurality of second semiconductor regions of the first conductivity type selectively provided in the second-conductivity-type epitaxial layer, a plurality of trenches penetrating through the second semiconductor regions and the second-conductivity-type epitaxial layer, and a plurality of gate electrodes provided in the trenches via gate insulating films. A lifetime of the minority carrier of the first semiconductor region is shorter than that of the rest of the second first-conductivity-type epitaxial layer.

According to one embodiment, a semiconductor device includes a first element region. The first element region includes first, second, and third semiconductor regions, and first, and second conductive layers. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the first conductive layer crosses a first direction from the second partial region toward the first partial region. The third partial region is between the second partial region and the second conductive layer in the second direction. The second semiconductor region includes a first semiconductor portion. The first semiconductor portion is between the first partial region and the first conductive layer in the second direction. At least a portion of the third semiconductor region is between the first partial region and the first semiconductor portion in the second direction.

A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells (40) and a pilot diode unit cell (50) comprising a second conductivity type anode region (51) in direct contact with a first main electrode (21) and extending from a first main side (11) to a first depth (d1). Each active unit cell (40) comprises a first conductivity type first source layer (41a) in direct contact with the first main electrode (21), a second conductivity type base layer (42) and a first gate electrode (47a), which is separated from the first source layer (41a) and the second conductivity type base layer (42) by a first gate insulating layer (46a) to form a first field effect transistor structure. A lateral size (w) of the anode region (51) in an orthogonal projection onto a vertical plane perpendicular to the first main side (11) is equal to or less than 1 μm. On a first lateral side surface of the anode region (51) a first insulating layer (52a) is arranged and on an opposing second lateral side surface of the anode region (51) a second insulating layer (52b) is arranged. And a distance between the first insulating layer (52a) and the second insulating layer (52b) is equal to or less than 1 μm, the first insulating layer (52a) extending vertically from the first main side (11) to a second depth (d2), and the second insulating layer (52b) extending vertically from the first main side (11) to a third depth (d3), wherein the first depth (d1) is less than the second depth (d2) and less than the third depth (d3).

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.

In a general aspect, a semiconductor device can include a semiconductor substrate, a trench formed in the semiconductor substrate and a first dielectric layer lining the trench. The semiconductor device can further include a first semiconductor material disposed in a lower portion of the trench. The first dielectric layer being can be disposed between the semiconductor substrate and the first semiconductor material. The semiconductor device can also include a second dielectric layer disposed on the first semiconductor material and a second semiconductor material disposed in an upper portion of the trench. The first dielectric layer can be disposed between the semiconductor substrate and the second semiconductor material. The second dielectric layer can be disposed between the first semiconductor material and the second semiconductor material. The semiconductor device can also include at least one of a diode or a resistor defined in the second semiconductor material.