A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

A semiconductor device includes a main element and a sensing element each including a drift region of a first conductivity-type, a well region of a second conductivity-type provided at an upper part of the drift region, a first main electrode region of the first conductivity-type provided at an upper part of the well region, a gate electrode buried with a gate insulating film interposed in a trench, and a main electrode connected to the first main electrode region, the isolation region including an element-isolation insulating film provided on a top surface of a semiconductor base body interposed between the well regions, and a first wire provided on a top surface of the element-isolation insulating film and electrically connected to the main electrode of the main element.

A semiconductor device includes a chip which has a first main surface on one side and a second main surface on the other side and which includes an active surface set at an inner portion of the first main surface and an outside surface set at a peripheral edge portion of the first main surface, a functional device which is formed at the active surface side, a projecting structure which includes an inorganic substance and projects at the outside surface side, and an organic film which covers the projecting structure.

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

A silicon carbide semiconductor device includes silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a trench, a gate insulating film, a gate electrode, and an interlayer insulating film. The first semiconductor layer and the second semiconductor layer constitute a first-conductivity-type semiconductor layer and in a deep region of the first-conductivity-type semiconductor layer at least 1 μm from an interface with the third semiconductor layer, a maximum value of a concentration of aluminum is less than 3.0×10.sup.13/cm.sup.3. In the deep region of the first-conductivity-type semiconductor layer, a maximum value of a concentration of boron is less than 1.0×10.sup.14/cm.sup.3.

A semiconductor device according to the present disclosure is an RC-IGBT in which an IGBT region 10 and a diode region 20 are provided adjacent to each other. The diode region 20 includes a p-type anode layer 25 provided on a first principal surface side of an n.sup.−-type drift layer 1, a p-type contact layer 24 provided on the first principal surface side of the p-type anode layer 25 and at a surface layer of a semiconductor substrate on the first principal surface side and connected with an emitter electrode 6, and an n.sup.+-type cathode layer 26 provided at a surface layer of the semiconductor substrate on a second principal surface side. The p-type contact layer 24 contains aluminum as p-type impurities, and the thickness of the p-type contact layer 24 is smaller than the thickness of an n.sup.+-type source layer 13 provided in the IGBT region 10.

A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a second electrode connected to the third and fourth semiconductor layers, a gate electrode extending from the fourth toward the second semiconductor layer next to the third semiconductor layer, a field plate electrode extending in a direction from the fourth toward the second semiconductor layer next to the second semiconductor layer, and a first insulating film between the field plate electrode and the second semiconductor layer and having a lower end further from the field plate electrode than the first semiconductor layer; the first, second, and fourth semiconductor layers are of a first conductivity type; and the third semiconductor layer is of a second conductivity type.

There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.

A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

A semiconductor device of an embodiment includes a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, and includes a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, in contact with the first electrode, containing an at least one element selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and containing at least one first atom of the at least one element, the first atom being bonded to four silicon atoms.