An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.

According to an aspect, an array substrate includes a first scan line, a second scan line, and a signal line. A semiconductor film has a coupling portion coupling one end of a first linear portion to one end of a second linear portion. Another end of the first linear portion of the semiconductor film and another end of the second linear portion of the semiconductor film are coupled to the signal line. In a plan view, the semiconductor film is disposed between the first scan line and the second scan line, the first linear portion intersects two first gate electrodes, and the second linear portion intersects two second gate electrodes.

A semiconductor device including at least an inversion channel region includes an oxide semiconductor film containing a crystal that contains at least gallium oxide at the inversion channel region.

A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

In a semiconductor device including first and second conductive plates (FFPs) formed by being stacked in layer, the first conductive plate and the second conductive plate include linear regions elongated to face each other along a longitudinal direction in which a length with which source region and drain region elongated in parallel face each other is longest, and are elongated in a short-side direction orthogonal to the longitudinal direction. Here, high voltage wiring of either one of source wiring and drain wiring is elongated in the short-side direction to intersect the linear regions of the first conductive plate and the second conductive plate, and low voltage wiring of the other one of source wiring and drain wiring is elongated in the short-side direction to intersect at least one linear region of the first conductive plate or the second conductive plate.

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high E.sub.crit semiconductors are presented. A dielectric layer is deposited on a high E.sub.crit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high E.sub.crit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high E.sub.crit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

Certain aspects of the present disclosure generally relate to a transistor having a self-aligned drift region and asymmetric spacers. One example transistor generally includes a channel region; a gate region disposed above the channel region; a first implant region; a second implant region having a same doping type as the first implant region, but a different doping type than the channel region; a first spacer disposed adjacent to a first side of the gate region; a second spacer disposed adjacent to a second side of the gate region and having a wider width than the first spacer; and a drift region having an edge vertically aligned with an edge of the second spacer and disposed between the channel region and the second implant region. The channel region may be disposed between the first implant region and the drift region.

The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.