An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer. When viewed in a normal direction of the substrate, the upper gate electrode does not overlap a first electrode which is one of the source electrode and the drain electrode, and a second electrode which is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.

A semiconductor device includes a P-type low potential region, an N-type first region, an N-type second region, an N-type third region, an annular trench, and a P-type isolation region. The N-type first region is provided on the principal surface of a P-type SOI layer provided to a P-type SOI substrate. The N-type first region has a concave portion. The N-type third region is provided inside the concave portion of the N-type first region so as to be away from the edge of the concave portion. A level-shift device is formed on the surface of the N-type third region. The P-type isolation region is a slit region extending in U-shape along the boundary between the N-type third region and the concave portion of the N-type first region.

An integrated circuit is described. The integrated circuit includes a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET is on a first surface of an insulator layer of the integrated circuit. The MOSFET including a source region, a drain region, and a front gate. The MOSFET also includes an extended drain region between the drain region and a well proximate the front gate. The integrated circuit also includes back gates on a second surface opposite the first surface of the insulator layer. The back gates are overlapped by the extended drain region.

A semiconductor structure that includes at least one lateral diffusion field effect transistor is described. The structure includes a source contact and a gate shield that enables the line width of an ohmic region that electrically connects the source/body region to the gate shield to be smaller than the minimum contact feature size. The gate shield defines a bottom recess for forming a narrower bottom portion of the source contact, and a section that flares outward with distance from the ohmic region to extend above and laterally beyond the ohmic region. By providing a wider area for the source contact, the flared portion of the gate shield allows the portion of the gate shield that contacts the ohmic region to be narrower than the minimum contact feature size. As a result, the cell pitch of the lateral diffusion field effect transistor can be reduced.

New device structure for single-legged Silicon-On-Insulator Metal-Oxide-Semiconductor (SOI MOS) transistor is presented. This new structure imposes a hard barrier for an Impact-Ionizations current and for transients due to Single-Event-Effects (SEE's) in Body to laterally conduct (or diffuse) to the Source through the Body/Source junction. It forces these currents to conduct instead to the Source through an alternate path made of highly conductive Silicide. This alternate path effectively suppresses the latch-up of the built-in parasitic Bipolar structure without necessitating the incorporation of Body-Tied-Source (BTS) into the device layout which is known to increase the device periphery without correspondingly scaling its device current.

A semiconductor device is provided. The semiconductor device includes a substrate, an oxide layer disposed over the substrate, and a first epitaxial layer disposed over the oxide layer. The first epitaxial layer has the first conductivity type. The semiconductor device also includes a second epitaxial layer disposed over the first epitaxial layer and a third epitaxial layer disposed over the second epitaxial layer. The second epitaxial layer has a second conductivity type that is opposite to the first conductivity type. The third epitaxial layer has the first conductivity type.

A thin-film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode. The gate electrode overlaps the active layer. The source electrode and the drain electrode are connected to the active layer. The active layer includes a source region connected to the source electrode, a drain region connected to the drain electrode, a channel region overlapping with the gate electrode, a first resistive region between the source region and the channel region, and a second resistive region between the drain region and the channel region. The length of the first resistive region is larger than the length of the second resistive region.

Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.

An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.