A crystal controlled oscillator includes a crystal unit, an integrated circuit, and an insulating resin. The crystal unit contains a crystal vibrating piece resonating at a predetermined frequency. The integrated circuit places the crystal unit. The integrated circuit includes an oscillator circuit oscillating the crystal vibrating piece. The insulating resin is formed to cover the crystal unit on the integrated circuit.

The present application discloses a method for fabricating a semiconductor device with slanted conductive layers. The method for fabricating a semiconductor device includes providing a substrate, forming a first insulating layer above the substrate, forming first slanted recesses along the first insulating layer, and forming first slanted conductive layers in the first slanted recesses and a top conductive layer covering the first slanted conductive layers.

A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

A semiconductor substrate has a back side surface and a front side surface. Metallization levels are provide at the front side surface. Capacitive deep trench isolation structures extend completely through the semiconductor substrate from the front side surface to the back side surface. Each capacitive deep trench isolation structure includes a conductive region insulated from the semiconductor substrate by an insulating liner. The conductive regions at first ends of the plurality of capacitive deep trench isolation structures are electrically connected to a first metallization level by electrical contacts. A bonding pad structure is located at the back side surface of the semiconductor substrate in direct physical and electrical connection to the conductive regions at second ends of the capacitive deep trench isolation structures.

Systems and methods taught herein provide thin film semiconductor devices such as thin film photovoltaic devices having via holes that enable electrical connection with a bottom surface of a topside contact of the thin film semiconductor device via the back side of the device (e.g., during mounting of the device). In some embodiments, the via holes are electrically insulated.

A memory device includes a first chip including a first electrode and a second chip including a second electrode. The first electrode includes a first conductive film having a first surface in contact with the second electrode at a boundary region of the first and second electrodes, a second surface spaced apart from the boundary region, and a third surface between the first surface and the second surface, and having a first portion on the first surface side and a second portion on the second surface side, and includes a second conductive film covering the second surface and the third surface of the first conductive film. A (111) orientation ratio of copper contained in the first portion is higher than a (111) orientation ratio of copper contained in the second portion.

A crystal controlled oscillator includes a crystal unit, an integrated circuit, and an insulating resin. The crystal unit contains a crystal vibrating piece resonating at a predetermined frequency. The integrated circuit places the crystal unit. The integrated circuit includes an oscillator circuit oscillating the crystal vibrating piece. The insulating resin is formed to cover the crystal unit on the integrated circuit.

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.