A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

A heat-dissipating structure is formed by bonding a first member and a second member, each being any of a metal, ceramic, and semiconductor, via a die bonding member; or a semiconductor module formed by bonding a semiconductor chip, a metal wire, a ceramic insulating substrate, and a heat-dissipating base substrate including metal, with a die bonding member interposed between each. At least one of the die bonding members includes a lead-free low-melting-point glass composition and metal particles. The lead-free low-melting-point glass composition accounts for 78 mol % or more in terms of the total of the oxides V2O5, TeO2, and Ag2O serving as main ingredients. The content of each of TeO2 and Ag2O is 1 to 2 times the content of V2O5, and at least one of BaO, WO3, and P2O5 is included as accessory ingredients, and at least one of Y2O3, La2O3, and Al2O3 is included as additional ingredients.

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm.sup.2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.

This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm.sup.2 (measurement: four point method, relative to temperature of 300K) and an optical transmittance greater than 0.8 (for a wavelength range from 400 nm to 1500 nm) on the first and second contact area.

A laminated chip includes: semiconductor chips that are laminated; and multiple types of adhesive insulating resin films that include mutually different characteristics and that are filled between the semiconductor chips, wherein the multiple types of the adhesive insulating resin films are arranged in a chip plane direction, depending on a demand characteristic for each region in a chip plane.

A laminated chip includes: semiconductor chips that are laminated; and multiple types of adhesive insulating resin films that include mutually different characteristics and that are filled between the semiconductor chips, wherein the multiple types of the adhesive insulating resin films are arranged in a chip plane direction, depending on a demand characteristic for each region in a chip plane.