A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

It is an object to provide a highly reliable physical-quantity measurement device which can relax thermal stress at a time of bonding and suppress creep or drift of a sensor output.

To attain the above-described object, a physical-quantity measurement device according to the present invention includes a semiconductor element, and a base board connected to the semiconductor element with a plurality of layers being interposed. In the plurality of layers, a stress relaxing layer including at least metal as a main ingredient and a glass layer including glass as a main ingredient are formed each in a layered form including one or more layers. At least one of the stress relaxing layer and the glass layer includes low-melting-point glass, and a softening point of the low-melting-point glass is equal to or lower than the highest heat temperature that the semiconductor element can resist.

A semiconductor device includes a metal body; a bonding layer placed on the metal body; and a semiconductor chip placed on the bonding layer. The bonding layer includes a filler-containing first layer formed between the metal body and the semiconductor chip and a second layer bonded to the first layer and the semiconductor chip. The second layer has a thermal expansion coefficient higher than that of the first layer.

Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed.

A semiconductor device includes a metal body; a bonding layer placed on the metal body; and a semiconductor chip placed on the bonding layer. The bonding layer includes a filler-containing first layer formed between the metal body and the semiconductor chip and a second layer bonded to the first layer and the semiconductor chip. The second layer has a thermal expansion coefficient higher than that of the first layer.

A power module substrate with a Ag underlayer of the invention includes: a circuit layer that is formed on one surface of an insulating layer; and a Ag underlayer that is formed on the circuit layer, in which the Ag underlayer is composed of a glass layer that is formed on the circuit layer side and a Ag layer that is formed by lamination on the glass layer, and regarding the Ag underlayer, in a Raman spectrum obtained by a Raman spectroscopy with incident light made incident from a surface of the Ag layer on a side opposite to the glass layer, when a maximum value of intensity in a wavenumber range of 3,000 cm.sup.1 to 4,000 cm.sup.1 indicated by I.sub.A, and a maximum value of intensity in a wavenumber range of 450 cm.sup.1 to 550 cm.sup.1 is indicated by I.sub.B, I.sub.A/I.sub.B is 1.1 or greater.

An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.

Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.