A semiconductor device includes an integrated circuit attached to a chip carrier in a flip chip configuration. A substrate extends to a back surface of the integrated circuit, and an interconnect region extends to a front surface of the integrated circuit. A substrate bond pad is disposed at the front surface, and is electrically coupled through the interconnect region to the semiconductor material. The chip carrier includes a substrate lead at a front surface of the chip carrier. The substrate lead is electrically coupled to the substrate bond pad. An electrically conductive compression sheet is disposed on the back surface of the integrated circuit, with lower compression tips making electrical contact with the semiconductor material in the substrate. The electrically conductive compression sheet is electrically coupled to the substrate lead of the chip carrier by a back surface shunt disposed outside of the integrated circuit.

A semiconductor package includes a first integrated circuit, a first passivation layer, a second passivation layer, a thermal pattern, an adhesive layer and a second integrated circuit. The first integrated circuit is encapsulated by an encapsulant. The first passivation layer is disposed over the first integrated circuit and the encapsulant. The second passivation layer is disposed over the first passivation layer. The thermal pattern is disposed in the first passivation layer and the second passivation layer. The adhesive layer is disposed over the second passivation layer and in direct contact with the thermal pattern. The second integrated circuit is adhered to the first integrated circuit through the adhesive layer.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

There is provided a pre-applied semiconductor sealing film for curing under pressure atmosphere as a non conductive film (NCF) suitable for pressure mounting. This NCF includes (A) a solid epoxy resin, (B) an aromatic amine which is liquid at room temperature and contains at least one of structures represented by formulae 1 and 2 below, (C) a silica filler, and (D) a polymer resin having a mass average molecular weight (Mw) of 6000 to 100000. The epoxy resin of the component (A) has an epoxy equivalent weight of 220 to 340. The component (B) is included in an amount of 6 to 27 parts by mass relative to 100 parts by mass of the component (A). The component (C) is included in an amount of 20 to 65 parts by mass relative to 100 parts by mass in total of the components. A content ratio ((A):(D)) between the component (A) and the component (D) is 99:1 to 65:35. This NCF further has a melt viscosity at 120° C. of 100 Pa.Math.s or less, and has a melt viscosity at 120° C., after heated at 260° C. or more for 5 to 90 seconds, of 200 Pa.Math.s or less.

There is provided a pre-applied semiconductor sealing film for curing under pressure atmosphere as a non conductive film (NCF) suitable for pressure mounting. This NCF includes (A) a solid epoxy resin, (B) an aromatic amine which is liquid at room temperature and contains at least one of structures represented by formulae 1 and 2 below, (C) a silica filler, and (D) a polymer resin having a mass average molecular weight (Mw) of 6000 to 100000. The epoxy resin of the component (A) has an epoxy equivalent weight of 220 to 340. The component (B) is included in an amount of 6 to 27 parts by mass relative to 100 parts by mass of the component (A). The component (C) is included in an amount of 20 to 65 parts by mass relative to 100 parts by mass in total of the components. A content ratio ((A):(D)) between the component (A) and the component (D) is 99:1 to 65:35. This NCF further has a melt viscosity at 120° C. of 100 Pa.Math.s or less, and has a melt viscosity at 120° C., after heated at 260° C. or more for 5 to 90 seconds, of 200 Pa.Math.s or less.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

A method for underfilling an electronic circuit assembly may include mounting one or more structures to a substrate, mounting one or more spacers to the substrate at one or more positions, respectively, to form one or more passages between the one or more spacers and the one or more structures, dispensing underfill to the one or more passages, and curing the underfill to secure the one or more structures to the substrate. The one or more structures may include one or more dies.

A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.