A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

A manufacturing method of an electronic-component-mounted module includes a step of forming a laminate of: a ceramic substrate board, a circuit layer made of aluminum or aluminum alloy on the ceramic substrate board, a first silver paste layer between the circuit layer and one surface of an electronic component, the electronic component, a lead frame made of copper or copper alloy, and a second silver paste layer between the other surface of the electronic component and the lead frame; and a step of batch-bonding bonding the circuit layer, the electronic component, and the lead frame at one time by heating the laminate to a heating temperature of not less than 180° C. to 350° C. inclusive with adding a pressure of 1 MPa to 20 MPa inclusive in a laminating direction on the laminate, to sinter the first and second silver paste layers and form first and second silver-sintered bonding layers.

A manufacturing method of an electronic-component-mounted module includes a step of forming a laminate of: a ceramic substrate board, a circuit layer made of aluminum or aluminum alloy on the ceramic substrate board, a first silver paste layer between the circuit layer and one surface of an electronic component, the electronic component, a lead frame made of copper or copper alloy, and a second silver paste layer between the other surface of the electronic component and the lead frame; and a step of batch-bonding bonding the circuit layer, the electronic component, and the lead frame at one time by heating the laminate to a heating temperature of not less than 180° C. to 350° C. inclusive with adding a pressure of 1 MPa to 20 MPa inclusive in a laminating direction on the laminate, to sinter the first and second silver paste layers and form first and second silver-sintered bonding layers.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.