A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

A package structure is provided. The package structure includes a redistribution structure and a semiconductor chip over the redistribution structure. The package structure also includes an adhesive element over the semiconductor chip. Opposite outermost edges of the adhesive element are laterally between opposite outermost edges of the redistribution structure. The package structure further includes a protective layer laterally surrounding the semiconductor chip and the adhesive element. In addition, the package structure includes a thermal conductive element over the semiconductor chip. The thermal conductive element is surrounded by the adhesive element.

A thermal management solution in a mobile computing system is bonded to an integrated circuit component by a thermal interface material layer (TIM layer) that does not require the application of a permanent force to ensure a reliable thermally conductive connection. A leaf spring or other loading mechanism that can apply a permanent force to a TIM layer can be secured to a printed circuit board by fasteners that extend through holes in the board in the vicinity of the integrated circuit component. These holes consume area that could otherwise be used for signal routing. In devices that use a TIM layer that does not require the application of a permanent force, the thermal management solution can be attached to a printed circuit board or chassis at a location remote to the integrated circuit component, where the attachment mechanism does not or minimally interferes with integrated circuit component signal routing.

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

A die and substrate assembly is disclosed for a die with electronic circuitry and a substrate. A sintered bonding layer of sintered metal is disposed between the die and the substrate. The sintered bonding layer includes a plurality of zones having different sintered metal densities. The plurality of zones are distributed along one or more horizontal axes of the sintered bonding layer, along one or more vertical axes of the sintered bonding layer or along both one or more horizontal and one or more vertical axes of the sintered bonding layer.

A die and substrate assembly is disclosed for a die with electronic circuitry and a substrate. A sintered bonding layer of sintered metal is disposed between the die and the substrate. The sintered bonding layer includes a plurality of zones having different sintered metal densities. The plurality of zones are distributed along one or more horizontal axes of the sintered bonding layer, along one or more vertical axes of the sintered bonding layer or along both one or more horizontal and one or more vertical axes of the sintered bonding layer.

Illustrative embodiments of anisotropic conductive adhesive (ACA) and associated methods are disclosed. In one illustrative embodiment, the ACA may comprise a binder curable using UV light and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material. The electrically conducting material may form electrically conductive and isolated parallel paths when the ACA is cured using UV light after being subjected to a magnetic field.

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.