A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.

A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.

Laminated composite (10) comprising at least one electronic substrate (11) and an arrangement of layers (20, 30) made up of at least a first layer (20) of a first metal and/or a first metal alloy and of a second layer (30) of a second metal and/or a second metal alloy adjacent to this first layer (20), wherein the melting temperatures of the first and second layers are different, and wherein, after a thermal treatment of the arrangement of layers (20, 30), a region with at least one intermetallic phase (40) is formed between the first layer and the second layer, wherein the first layer (20) or the second layer (30) is formed by a reaction solder which consists of a mixture of a basic solder with an AgX, CuX or NiX alloy, wherein the component X of the AgX, CuX or NiX alloy is selected from the group consisting of B, Mg, Al, Si, Ca, Se, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Ag, In, Sn, Sb, Ba, Hf, Ta, W, Au, Bi, La, Ce, Pr, Nd, Gd, Dy, Sm, Er, Tb, Eu, Ho, Tm, Yb and Lu and wherein the melting temperature of the AgX, CuX or NiX alloy is greater than the melting temperature of the basic solder. The invention also relates to a method for forming a laminated composite (10) and to a circuit arrangement containing a laminated composite (10) according to the invention.

A joined structure includes: a first member; and a second member that faces the first member and that is joined to the first member via a joining layer. The joining layer includes a metal material and a solder material, apart of the metal material has at least one pore, and the solder material is located in a part of an internal area of the at least one pore. Also disclosed is a joining method that makes it possible to produce the joined structure. Further disclosed is a joining material used in the joining method. The joining method makes it possible to achieve non-pressurization sintering processes while maintaining high precise thickness of a joining layer between the first layer and the second layer based on the spacer.

Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.

Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.

A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y11 mass %, x+14y42 mass %, and x5.1 mass %.